riscv u-boot的hart_lottery机制

之前一直没理解riscv u-boot的hart_lottery机制,
今天仔细看了一下，将其分析放在这儿：
u-boot\arch\riscv\cpu\start.s中

la t0, hart_lottery
li s2, 1
//li t1, 1
amoswap.w.aqrl s2, t1, 0(t0)
bnez s2, wait_for_gd_init
#else
bnez tp, secondary_hart_loop
#endif

#ifdef CONFIG_OF_PRIOR_STAGE
la t0, prior_stage_fdt_address
SREG s1, 0(t0)
#endif

jal	board_init_f_init_reserve

/* save the boot hart id to global_data */
SREG	tp, GD_BOOT_HART(gp)

#ifndef CONFIG_XIP
la t0, available_harts_lock
fence rw, w
amoswap.w.aqrl zero, zero, 0(t0)

wait_for_gd_init:
la t0, available_harts_lock
li t1, 1
1: amoswap.w.aqrl t1, t1, 0(t0)
fence r, rw
bnez t1, 1b

u-boot\arch\riscv\cpu\cpu.c中
u32 hart_lottery attribute((section(“.data”))) = 0;
//u32 hart_lottery=0;
/*

• The main hart running U-Boot has acquired available_harts_lock until it has
• finishe