STM32未使用引脚的处理方式及推荐硬件设计规范

STM32在不完全使用所有资源的情况下,为了提高EMC性能,应将未使用的I/O设置为“0”或“1”,并禁用未使用的功能。推荐的硬件设计包括使用多层PCB,分离地线和电源层,以及良好的接地和电源供应布局。组件位置应根据其EMI贡献进行分离,以减少PCB上的交叉耦合。每个电源供应对需要适当的解耦,且所有未使用的PCB区域应填充额外的接地,以提供屏蔽效果。
AI助手已提取文章相关产品:
引用原文(AN2586)

All microcontrollers are designed for a variety of applications and often a particular application does not use 100% of the MCU resources.

To increase EMC performance, unused clocks, counters or I/Os, should not be left free, e.g.I/Os should be set to “0” or “1”(pull-up or pull-down to the unused I/O pins.) and unusedfeatures should be “frozen” or disabled.

顺带将其他相关推荐设计摘录如下:
5.1 Printed circuit board
For technical reasons, it is best to use a multilayer printed circuit board (PCB) with a separate layer dedicated to ground (VSS) and another dedicated to the VDD supply. This provides good decoupling and a good shielding effect. For many applications, economical reasons prohibit the use of this type of board. In this case, the major requirement is to ensure a good structure for ground and for the power supply.

5.2 Component position
A preliminary layout of the PCB must separate the different circuits according to their EMI contribution in order to reduce cross-coupling on the PCB, that is noisy, high-current circuits,low-voltage circuits, and digital components.

5.3 Ground and power supply (VSS, VDD)
Every block (noisy, low-level sensitive, digital, etc.) should be grounded individually and all ground returns should be to a single point. Loops must be avoided or have a minimum area.The power supply should be implemented close to the ground line to minimize the area of the supply loop. This is due to the fact that the supply loop acts as an antenna, and is therefore the main transmitter and receiver of EMI. All component-free PCB areas must be filled with additional grounding to create a kind of shielding (especially when using singlelayer PCBs).

5.4 Decoupling
All pins need to be properly connected to the power supplies. These connections, including pads, tracks and vias should have as low an impedance as possible. This is typically achieved with thick track widths and, preferably, the use of dedicated power supply planes in multilayer PCBs. In addition, each power supply pair should be decoupled with filtering ceramic capacitors C (100 nF) and a chemical capacitor C of about 10 μF connected in parallel on the STM32F10xxx device. These capacitors need to be placed as close as possible to, or below,the appropriate pins on the underside of the PCB. Typical values are 10 nF to 100 nF, but exact values depend on the application needs. Figure 13 shows the typical layout of such a VDD/VSS pair.
STM32未使用引脚的处理方式及推荐硬件设计规范 - kanku - kanku的博客
 Figure 13. Typical layout for VDD/VSS pair

5.5 Other signals
When designing an application, the EMC performance can be improved by closely studying:
● sigNals for which a temporary disturbance affects the running process permanently (the case of interrupts and handshaking strobe signals, and not the case for LEDcommands).For these signals, a surrounding ground trace, shorter lengths and the absence of noisy and sensitive traces nearby (crosstalk effect) improve EMC performance.For digital signals, the best possible electrical margin must be reached for the two
logical states and slow Schmitt triggers are recommended to eliminate parasitic states.
● Noisy signals (clock, etc.)
● Sensitive signals (high impedance, etc.)

您可能感兴趣的与本文相关内容

评论
添加红包

请填写红包祝福语或标题

红包个数最小为10个

红包金额最低5元

当前余额3.43前往充值 >
需支付:10.00
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明:

1.余额是钱包充值的虚拟货币,按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载,可以购买VIP、付费专栏及课程。

余额充值