Sabrewing Issues

原创于 2012-05-25 10:37:28 发布 · 579 阅读

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本文介绍了一种名为Sabrewing的设计在FPGA和ASIC技术中的实现过程。该设计采用VHDL进行结构描述，并通过Synopsys Synplify进行了FPGA映射，目标设备为Virtex-5 LX330T。对于ASIC原型，使用了Synopsys Design Compiler进行综合，Cadence Encounter用于布局生成。此外，还评估了STMicroelectronics提供的65nm CMOS技术中的两种不同库。

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1.http://www.hipeac.net/conference/paris/papertrack

2.To show the feasibility and advantages of Sabrewing, a VHDL structural description has been implemented in FPGA and ASIC technology. FPGA mapping was carried out using Synopsys Synplify, targeting a Virtex-5 LX330T device. The ASIC prototype is based on a fairly standard IC design ?ow, using Synopsys DesignCompiler for synthesis and Cadence Encounter for layout generation. Both the low-power high voltage threshold (LPHVT) and general-purpose standard voltage threshold (GPSVT) libraries from STMicroelectronics’ 65nm CMOS technology have been evaluated.