yl2021的博客

HDLBITS: writing testbenches

yl2021 — Tue, 01 Mar 2022 20:12:59 +0800

You are provided a module with the following declaration: module dut ( input clk ) ; Write a testbench that creates one instance of module dut (with any instance name), and create a clock signal to drive the module's clkinput. The clock has a period of

Bulid a circuits from simulation waveform

yl2021 — Mon, 28 Feb 2022 14:56:14 +0800

This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it. module top_module ( input a, input b, output q );// assign q = a&b; // Fix me endmodule This is a combina.

Finding bugs in code

yl2021 — Sat, 26 Feb 2022 16:31:43 +0800

This 8-bit wide 2-to-1 multiplexer doesn't work. Fix the bug(s). module top_module ( input sel, input [7:0] a, input [7:0] b, output out ); assign out = (~sel & a) | (sel & b); endmodule 从上面的代码中我们可以看到，输出的out信号位宽不对，其次多路选择的表

Building larger circuit

yl2021 — Wed, 23 Feb 2022 14:30:35 +0800

Build a counter that counts from 0 to 999, inclusive, with a period of 1000 cycles. The reset input is synchronous, and should reset the counter to 0. module top_module ( input clk, input reset, output [9:0] q); always @(posedge clk) be

Finite State Machines

yl2021 — Sun, 13 Feb 2022 14:57:33 +0800

This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B. This exercise is the same asfsm1s, but using asynchronous reset.

Sequential Logic-more circuits(feel free to look)

yl2021 — Sat, 12 Feb 2022 14:50:43 +0800

At each time step, the next state of each cell is the XOR of the cell's two current neighbours. A more verbose way of expressing this rule is the following table, where a cell's next state is a function of itself and its two neighbours: Left Center

Sequential Logic-Counters

yl2021 — Fri, 11 Feb 2022 13:54:23 +0800

Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is synchronous, and should reset the counter to 0. module top_module ( input clk, input reset, // Synchronous active-high reset

Sequential logic-shift registers

yl2021 — Wed, 26 Jan 2022 15:05:37 +0800

构建一个4bit的移位寄存器(右移)，含异步复位、同步加载和使能 areset：让寄存器复位为0 load：加载4bit数据到移位寄存器中，不移位 ena：使能右移 q：移位寄存器中的内容 module top_module( input clk, input areset, // async active-high reset to zero input load, input ena, input [3:0] data, output r

Sequential Logic-Latchs and Flip-Flops

yl2021 — Tue, 25 Jan 2022 14:26:09 +0800

D触发器： module top_module ( input clk, // Clocks are used in sequential circuits input d, output reg q );// always @(posedge clk) begin q<=d; end // Use a clocked always block // copy d to q at every positive

组合逻辑电路-karnaugh map to circuit卡洛图

yl2021 — Tue, 04 Jan 2022 17:03:05 +0800

Implement the circuit described by the Karnaugh map below. module top_module( input a, input b, input c, output out ); assign out = (a | b | c); endmodule Implement the circuit described by the Karnaugh map below. module .

组合逻辑电路-arithmetic circuits

yl2021 — Mon, 03 Jan 2022 16:56:58 +0800

Create a half adder. A half adder adds two bits (with no carry-in) and produces a sum and carry-out. module top_module( input a, b, output cout, sum ); assign sum=a^b; assign cout=a&b;//{cout,sum}=a+b; endmodule Create a full add

组合逻辑电路-multiplexer多路复用器

yl2021 — Mon, 03 Jan 2022 15:32:44 +0800

Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b. module top_module( input a, b, sel, output out ); assign out = sel?b:a; endmodule Create a 100-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When se

组合逻辑电路-basic gates

yl2021 — Fri, 31 Dec 2021 16:39:29 +0800

wire： Implement the following circuit: module top_module ( input in, output out); assign out=in; endmodule gnd： Implement the following circuit: module top_module ( output out); assign out=1'b0; endmodule NOR: Implement the fol

verilog基础others

yl2021 — Thu, 30 Dec 2021 16:51:34 +0800

Conditional：条件运算符 Verilog has a ternary conditional operator (?: ) much like C: (condition? if_true: if_false) This can be used to choose one of two values based on condition (a mux!) on one line, without using an if-then inside a combinational al...

verilog基础过程化

yl2021 — Wed, 29 Dec 2021 16:36:18 +0800

Alwaysblock1： Since digital circuits are composed of logic gates connected with wires, any circuit can be expressed as some combination of modules and assign statements. However, sometimes this is not the most convenient way to describe the circuit. Proce

verilog基础Module层次化

yl2021 — Tue, 28 Dec 2021 16:49:23 +0800

Module： module mod_a ( input in1, input in2, output out ); // Module body endmodule Connecting Signals to Module Ports There are two commonly-used methods to connect a wire to a port: by position or by name. By position mod_a instance1 ( wa, w

verilog基础2Vector向量

yl2021 — Thu, 28 Oct 2021 15:28:34 +0800

Vector0： wire [99:0] my_vector; // Declare a 100-element vector assign out = my_vector[10]; // Part-select one bit out of the vector module top_module ( input wire [2:0] vec, output wire [2:0] outv, output wire o2, output wire o1,

常用的网址

yl2021 — Thu, 28 Oct 2021 14:12:22 +0800

HDLBitshttps://hdlbits.01xz.net/wiki/Main_Page

verilog基础1

yl2021 — Wed, 06 Oct 2021 16:00:15 +0800

module top_module ( input in, // Declare an input wire named "in" output out // Declare an output wire named "out" ); wire not_in; // Declare a wire named "not_in" assign out = ~not_in; // Assign a value.