Verilog语言——8路彩灯控制器

设计一个8路彩灯控制器，要求实现如下花样：
（1）从左到右逐个亮，从右到左逐个灭；
（2）从两边往中间逐个亮，从中间往两边逐个灭；
（3）重复上面1、2。

文本文件：

module caideng(clk,light,res);

input clk,res;

output[3:0] light;

reg[3:0] state;

reg[3:0] light;

parameter

FIRST=4'd0,

A=4'd1,  B=4'd2,

C=4'd3,  D=4'd4,

E=4'd5,  F=4'd6,

G=4'd7,  H=4'd8,

I=4'd9,  J=4'd10,

K=4'd11, L=4'd12;

                                  

always @(posedge clk)

begin

if(!res)

       begin

       state=FIRST;

       end

else

       casex(state)

       FIRST:state<=A;

       A:begin

              light=4'b1000;

              state<=B;

         end

       B:begin

              light=4'b1100;

              state<=C;

         end

       C:begin

              light=4'b1110;

              state<=D;

         end

       D:begin

              light=4'b1111;

              state<=E;

         end

       E:begin

              light=4'b1110;

              state<=F;

         end

       F:begin

              light=4'b1100;

              state<=G;

         end

       G:begin

              light=4'b1000;

              state<=H;

         end

       H:begin

              light=4'b0000;

              state<=I;

         end

       I:begin

              light=4'b1001;

              state<=J;

         end

       J:begin

              light=4'b1111;

              state<=K;

         end

       K:begin

              light=4'b1001;

              state<=L;

         end

       L:begin

              light=4'b0000;

              state<=A;

         end

       default:state=FIRST;

       endcase

       end

endmodule