<?xml version="1.0" encoding="utf-8" ?><rss version="2.0"><channel><title><![CDATA[wickedwtq的博客]]></title><description><![CDATA[]]></description><link>https://blog.youkuaiyun.com/wickedwtq</link><language>zh-cn</language><generator>https://blog.youkuaiyun.com/</generator><copyright><![CDATA[Copyright &copy; wickedwtq]]></copyright><item><title><![CDATA[再次探索定点数——单个信号的缩放和多个信号的叠加]]></title><link>https://blog.youkuaiyun.com/wickedwtq/article/details/72644015</link><guid>https://blog.youkuaiyun.com/wickedwtq/article/details/72644015</guid><author>wickedwtq</author><pubDate>Tue, 23 May 2017 16:03:25 +0800</pubDate><description><![CDATA[1、正弦信号的合成1.1 signal tap]]></description><category></category></item><item><title><![CDATA[探索 DDS 和 EDA 工具]]></title><link>https://blog.youkuaiyun.com/wickedwtq/article/details/70738947</link><guid>https://blog.youkuaiyun.com/wickedwtq/article/details/70738947</guid><author>wickedwtq</author><pubDate>Tue, 25 Apr 2017 14:24:03 +0800</pubDate><description><![CDATA[探索 DDS 和 EDA 工具]]></description><category></category></item><item><title><![CDATA[探索定点数]]></title><link>https://blog.youkuaiyun.com/wickedwtq/article/details/67636197</link><guid>https://blog.youkuaiyun.com/wickedwtq/article/details/67636197</guid><author>wickedwtq</author><pubDate>Tue, 25 Apr 2017 13:42:41 +0800</pubDate><description><![CDATA[探索定点数]]></description><category></category></item><item><title><![CDATA[helloworld：基于Qsys的第一个Nios II系统设计]]></title><link>https://blog.youkuaiyun.com/wickedwtq/article/details/69817455</link><guid>https://blog.youkuaiyun.com/wickedwtq/article/details/69817455</guid><author>wickedwtq</author><pubDate>Sun, 09 Apr 2017 15:03:21 +0800</pubDate><description><![CDATA[实现FPGA平台上的“Hello World”]]></description><category></category></item><item><title><![CDATA[作业3：DDS]]></title><link>https://blog.youkuaiyun.com/wickedwtq/article/details/54582181</link><guid>https://blog.youkuaiyun.com/wickedwtq/article/details/54582181</guid><author>wickedwtq</author><pubDate>Tue, 17 Jan 2017 13:26:13 +0800</pubDate><description><![CDATA[DDS]]></description><category></category></item><item><title><![CDATA[作业2：计数器数码管显示]]></title><link>https://blog.youkuaiyun.com/wickedwtq/article/details/53446845</link><guid>https://blog.youkuaiyun.com/wickedwtq/article/details/53446845</guid><author>wickedwtq</author><pubDate>Mon, 05 Dec 2016 10:52:21 +0800</pubDate><description><![CDATA[第二次作业，数码管显示]]></description><category></category></item><item><title><![CDATA[计数器模块]]></title><link>https://blog.youkuaiyun.com/wickedwtq/article/details/53365783</link><guid>https://blog.youkuaiyun.com/wickedwtq/article/details/53365783</guid><author>wickedwtq</author><pubDate>Mon, 28 Nov 2016 20:12:02 +0800</pubDate><description><![CDATA[计数器模块：
简单的0-9计数器
时间基准电路 和 带使能的多周期计数器
带清零和暂停功能的0-9.9s秒表]]></description><category></category></item><item><title><![CDATA[译码器模块]]></title><link>https://blog.youkuaiyun.com/wickedwtq/article/details/53364041</link><guid>https://blog.youkuaiyun.com/wickedwtq/article/details/53364041</guid><author>wickedwtq</author><pubDate>Sun, 27 Nov 2016 18:11:33 +0800</pubDate><description><![CDATA[3-8译码器（控制LED）
4-7译码器（控制数码管）]]></description><category></category></item><item><title><![CDATA[quartus常见错误集锦]]></title><link>https://blog.youkuaiyun.com/wickedwtq/article/details/53218939</link><guid>https://blog.youkuaiyun.com/wickedwtq/article/details/53218939</guid><author>wickedwtq</author><pubDate>Thu, 24 Nov 2016 20:43:29 +0800</pubDate><description><![CDATA[Error: Top-level design entity “Verilog1” is undefined

原因：顶层模块的module名没有和工程名同名 
解决方法：把顶层模块 module名改成和工程名同名，菜单Assignments -> Settings… 
打开后点击第一个General选项里，在Top-level entity标签指示下的编辑框里输入你的VHDL文本里的实体名字就O]]></description><category></category></item><item><title><![CDATA[作业1：计数器仿真实验作业]]></title><link>https://blog.youkuaiyun.com/wickedwtq/article/details/53149734</link><guid>https://blog.youkuaiyun.com/wickedwtq/article/details/53149734</guid><author>wickedwtq</author><pubDate>Sun, 13 Nov 2016 16:31:17 +0800</pubDate><description><![CDATA[计数器在电路复位后会循环的从0值递增计数到最大值，计数最大值是一个循环变化的过程，计数器复位之后，第一次计数最大值是6，然后是7、8、9，然后计数最大值又变成6，如此往复循环。]]></description><category></category></item><item><title><![CDATA[欢迎使用优快云-markdown编辑器]]></title><link>https://blog.youkuaiyun.com/wickedwtq/article/details/53149441</link><guid>https://blog.youkuaiyun.com/wickedwtq/article/details/53149441</guid><author>wickedwtq</author><pubDate>Sun, 13 Nov 2016 15:51:12 +0800</pubDate><description><![CDATA[欢迎使用Markdown编辑器写博客本Markdown编辑器使用StackEdit修改而来，用它写博客，将会带来全新的体验哦：
Markdown和扩展Markdown简洁的语法
代码块高亮
图片链接和图片上传
LaTex数学公式
UML序列图和流程图
离线写博客
导入导出Markdown文件
丰富的快捷键
快捷键
加粗    Ctrl + B 
斜体    Ctrl + I 
引用    Ctrl]]></description><category></category></item></channel></rss>