蓝桥杯FPGA赛道模拟题1之程序设计题代码

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已于 2025-03-15 14:45:13 修改 · 2.1k 阅读

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#蓝桥杯 #fpga开发 #职场和发展

于 2025-03-15 14:43:52 首次发布

1.顶层文件

module test(
input  wire sys_clk,
input  wire sys_rst,
input  wire [3:0]key_in,
output wire [7:0]sel,
output wire [7:0]seg,
output reg  [7:0]led

);
//定义状态
localparam STOP=3'd0;
localparam START=3'd1;
localparam PAUSE=3'd2;
//signals define
wire [4:0]  d_count;
wire [3:0]   key_data;
reg  [31:0] data;
reg    en_count;
reg    rst_count;
reg  [2:0] st_count;
reg  [7:0] u_count1;
reg   [7:0] u_count2;
reg   [23:0]led_count;

cdown cdown_inst(
.sys_clk  (sys_clk  ),
.sys_rst  (sys_rst  ),
.count_en  (en_count),
.count_rst  (rst_count),
.count     (d_count)
);

seg seg_inst(
	.clk      (sys_clk),
	.rst      (sys_rst),
	.seg      (seg),
	.sel      (sel),
	.dsp_data (data)
	);
key key_inst(
	.sys_clk (sys_clk),
	.sys_rst (sys_rst),
	.key_in  (key_in),
	.key_data (key_data)
);
//LED 
always @(posedge sys_clk or negedge sys_rst)begin
	if(sys_rst==1'b0)begin
		led<=8'b1111_1111;
		led_count<=0;
	end else begin
		if(st_count==STOP)//停止状态
		  led<=8'b1111_1111;
		else if(st_count==START)//开始状态灯亮
		  led<=8'b1111_1110;  
		else begin
		   if(led_count==24'd5_000_000)begin 
			led_count<=0;
			led<=led ^ 8'b0000_0001;//led灯每隔0.01秒闪烁
	    end else
			led_count<=led_count+1;
		end
	end
end 

//seg
always @(posedge sys_clk or negedge sys_rst)begin
	if(sys_rst==1'b0)
	data <={4'd2,4'd0,4'd10,4'd0,4'd0,4'd11,4'd0,4'd0};
	else begin
		data[31:28]<=d_count/10;
		data[27:24]<=d_count%10;
		data[19:16]<=u_count1/10;
		data[15:12]<=u_count1%10;
		data[7:4]<=u_count2/10;
		data[3:0]<=u_count2%10;
	end 
end 
//KEY
always @(posedge sys_clk or negedge sys_rst)begin
     if(sys_rst==1'b0)begin
	  u_count1<=8'b0;
	  u_count2<=8'b0;
	  en_count<=1'b0;
	  st_count<=STOP;
	end else b