<?xml version="1.0" encoding="utf-8" ?><rss version="2.0"><channel><title><![CDATA[weixin_44048021的博客]]></title><description><![CDATA[]]></description><link>https://blog.youkuaiyun.com/weixin_44048021</link><language>zh-cn</language><generator>https://blog.youkuaiyun.com/</generator><copyright><![CDATA[Copyright &copy; weixin_44048021]]></copyright><item><title><![CDATA[Verilog实现流水线]]></title><link>https://blog.youkuaiyun.com/weixin_44048021/article/details/129104972</link><guid>https://blog.youkuaiyun.com/weixin_44048021/article/details/129104972</guid><author>weixin_44048021</author><pubDate>Sat, 18 Feb 2023 21:42:14 +0800</pubDate><description><![CDATA[流水线verilog实现]]></description><category></category></item><item><title><![CDATA[源码 vivado调用FIFO 及仿真]]></title><link>https://blog.youkuaiyun.com/weixin_44048021/article/details/127414068</link><guid>https://blog.youkuaiyun.com/weixin_44048021/article/details/127414068</guid><author>weixin_44048021</author><pubDate>Wed, 19 Oct 2022 19:24:56 +0800</pubDate><description><![CDATA[【代码】源码 vivado调用FIFO 及仿真。]]></description><category></category></item><item><title><![CDATA[源码 vivado ram调用与仿真]]></title><link>https://blog.youkuaiyun.com/weixin_44048021/article/details/127407378</link><guid>https://blog.youkuaiyun.com/weixin_44048021/article/details/127407378</guid><author>weixin_44048021</author><pubDate>Wed, 19 Oct 2022 14:44:30 +0800</pubDate><description><![CDATA[【代码】源码 vivado ram调用与仿真。]]></description><category></category></item><item><title><![CDATA[vivado PLL调用]]></title><link>https://blog.youkuaiyun.com/weixin_44048021/article/details/127404193</link><guid>https://blog.youkuaiyun.com/weixin_44048021/article/details/127404193</guid><author>weixin_44048021</author><pubDate>Wed, 19 Oct 2022 11:15:13 +0800</pubDate><description><![CDATA[【代码】vivado PLL调用。]]></description><category></category></item><item><title><![CDATA[锁存器与触发器]]></title><link>https://blog.youkuaiyun.com/weixin_44048021/article/details/127342443</link><guid>https://blog.youkuaiyun.com/weixin_44048021/article/details/127342443</guid><author>weixin_44048021</author><pubDate>Sat, 15 Oct 2022 23:32:34 +0800</pubDate><description><![CDATA[latch flip_flop]]></description><category></category></item><item><title><![CDATA[调用OpenCV显示图片出错：terminate called after throwing an instance of ‘cv::Exception‘]]></title><link>https://blog.youkuaiyun.com/weixin_44048021/article/details/125760718</link><guid>https://blog.youkuaiyun.com/weixin_44048021/article/details/125760718</guid><author>weixin_44048021</author><pubDate>Wed, 13 Jul 2022 11:57:44 +0800</pubDate><description><![CDATA[调用OpenCV显示图片出错：terminate called after throwing an instance of 'cv::Exception']]></description><category></category></item><item><title><![CDATA[failed to load module “canberra-gtk-module“]]></title><link>https://blog.youkuaiyun.com/weixin_44048021/article/details/125760539</link><guid>https://blog.youkuaiyun.com/weixin_44048021/article/details/125760539</guid><author>weixin_44048021</author><pubDate>Wed, 13 Jul 2022 11:40:04 +0800</pubDate><description><![CDATA[failed to load module "canberra-gtk-module"]]></description><category></category></item><item><title><![CDATA[Sophus编译出错：lvalue required as left operand of assignment]]></title><link>https://blog.youkuaiyun.com/weixin_44048021/article/details/125728036</link><guid>https://blog.youkuaiyun.com/weixin_44048021/article/details/125728036</guid><author>weixin_44048021</author><pubDate>Mon, 11 Jul 2022 19:00:34 +0800</pubDate><description><![CDATA[Sophus编译出错：lvalue required as left operand of assignment]]></description><category></category></item><item><title><![CDATA[terminate called after throwing an instance of ‘std::runtime_error‘ what(): Pangolin X11: Failed]]></title><link>https://blog.youkuaiyun.com/weixin_44048021/article/details/125715809</link><guid>https://blog.youkuaiyun.com/weixin_44048021/article/details/125715809</guid><author>weixin_44048021</author><pubDate>Mon, 11 Jul 2022 18:57:23 +0800</pubDate><description><![CDATA[视觉SLAM14讲运行可视化程序出错]]></description><category></category></item><item><title><![CDATA[1101序列检测器，基于Verilog HDL]]></title><link>https://blog.youkuaiyun.com/weixin_44048021/article/details/125319514</link><guid>https://blog.youkuaiyun.com/weixin_44048021/article/details/125319514</guid><author>weixin_44048021</author><pubDate>Thu, 16 Jun 2022 17:12:35 +0800</pubDate><description><![CDATA[基于verilog的1101序列检测器]]></description><category></category></item><item><title><![CDATA[vivado执行报错number of unplaced terminals is greater than number of available sites]]></title><link>https://blog.youkuaiyun.com/weixin_44048021/article/details/124932711</link><guid>https://blog.youkuaiyun.com/weixin_44048021/article/details/124932711</guid><author>weixin_44048021</author><pubDate>Mon, 23 May 2022 18:54:30 +0800</pubDate><description><![CDATA[如图，报错！

原因是约束文件有错！仔细！更改后再执行就好了。








]]></description><category></category></item><item><title><![CDATA[阻塞式与非阻塞式的区别仿真]]></title><link>https://blog.youkuaiyun.com/weixin_44048021/article/details/123740355</link><guid>https://blog.youkuaiyun.com/weixin_44048021/article/details/123740355</guid><author>weixin_44048021</author><pubDate>Fri, 25 Mar 2022 17:02:31 +0800</pubDate><description><![CDATA[阻塞式源代码：


module block(
	//input 
	clk,
	rst_n,
	//output 
	result_o,
	a,
	b 
);
input clk,rst_n;

output reg [4:0] result_o;
output reg [3:0] a,b;
always @(posedge clk )
	begin 
		if(!rst_n)
			begin
				a = 4'd0;
				b = 4'd0;
			end 
		else 
			begin 
	]]></description><category></category></item><item><title><![CDATA[基于FPGA的频率测量]]></title><link>https://blog.youkuaiyun.com/weixin_44048021/article/details/123526251</link><guid>https://blog.youkuaiyun.com/weixin_44048021/article/details/123526251</guid><author>weixin_44048021</author><pubDate>Wed, 16 Mar 2022 14:49:43 +0800</pubDate><description><![CDATA[正弦波由matlb产生；


clc;
clear all;
close all;
%Sin400hz.m程序清单
%设置系统参数
fi=400;					%输入信号的频率
Fs=8000;				%采样频率
L=10024;				%数据长度
N=10;					%量化位数
x=0:1/(100*fi):2/fi;
figure('name','sin(2*pi*fi*x)');
plot(x,sin(2*pi*fi*x));
title('sin(2*pi*fi*x)');
xlabel('x');
y]]></description><category></category></item><item><title><![CDATA[基于FPGA的3-8译码器]]></title><link>https://blog.youkuaiyun.com/weixin_44048021/article/details/123428467</link><guid>https://blog.youkuaiyun.com/weixin_44048021/article/details/123428467</guid><author>weixin_44048021</author><pubDate>Fri, 11 Mar 2022 16:35:07 +0800</pubDate><description><![CDATA[源代码：


module decoder38(
	A,
	B,
	C,
	en,
	Y
);
input A,B,C,en;
output reg [7:0] Y;
always @(*)
begin
	if(!en)
		Y &lt;= 8'd0;
	else
		begin
			case({C,B,A})
				3'b000:Y &lt;= 8'b0000_0001;
				3'b001:Y &lt;= 8'b0000_0010;
				3'b010:Y &lt;= 8'b0000_0100;]]></description><category></category></item><item><title><![CDATA[基于matlab的滤波器系数量化处理]]></title><link>https://blog.youkuaiyun.com/weixin_44048021/article/details/123408917</link><guid>https://blog.youkuaiyun.com/weixin_44048021/article/details/123408917</guid><author>weixin_44048021</author><pubDate>Thu, 10 Mar 2022 19:16:32 +0800</pubDate><description><![CDATA[%filtercoequant.m
%调用filtercompare0函数生成滤波器系数；
h_pm = filtercompare0;
%将生成的滤波器系数数据写入FPGA所需的txt文件中。
fid = fopen('D:\matalb_dw\filtercoequant\m\lpf.txt','w');
%fopen:将数据按指定格式读入到matlab中的函数
%fid:file ID,文件代号，
    %返回值为+N，即正整数表示文件打开成功，文件代号是N
    %返回值为-1，表示文件打开不.]]></description><category></category></item><item><title><![CDATA[FIR滤波器matlab实现；三种滤波器比较。]]></title><link>https://blog.youkuaiyun.com/weixin_44048021/article/details/123374643</link><guid>https://blog.youkuaiyun.com/weixin_44048021/article/details/123374643</guid><author>weixin_44048021</author><pubDate>Wed, 09 Mar 2022 12:44:45 +0800</pubDate><description><![CDATA[FIR低通滤波器过滤带300-600Hz，采样频率8000Hz，通带、阻带纹波0.04，截止频率600Hz。


%《锁相环技术原理及FPGA实现-杜勇》第100页。
%filtercompare.m
%用kaiserord计算满足性能要求的最小滤波器阶数；
%用firpm和firm1分别设计最优滤波器，以及窗函数滤波器，并绘制其幅频特性
%输出最优滤波器系数

function h_pm = filtercompare0;
clc;
clear all;
close all;
fs = 8000;%采样频]]></description><category></category></item><item><title><![CDATA[matlab仿真运算中的字长效应]]></title><link>https://blog.youkuaiyun.com/weixin_44048021/article/details/123293041</link><guid>https://blog.youkuaiyun.com/weixin_44048021/article/details/123293041</guid><author>weixin_44048021</author><pubDate>Sat, 05 Mar 2022 12:55:31 +0800</pubDate><description><![CDATA[%仿真运算中的字长效应
clc;
clear all;
close all;
x=[7/8 zeros(1,15)];%一维数组，第一个值为7/8，剩下15个为0；
y=zeros(1,length(x));%zeros：产生一个1行，length(x)列的0矩阵；
Qy=zeros(1,length(x));%存放未量化运算结果
Qy2=zeros(1,length(x));%存放2bit量化运算结果
Qy4=zeros(1,length(x));%存放4bit量化运算结果
Qy6=zeros(1,le.]]></description><category></category></item><item><title><![CDATA[verilog中unsigned与signed加法结果的比较（带源码）]]></title><link>https://blog.youkuaiyun.com/weixin_44048021/article/details/123286993</link><guid>https://blog.youkuaiyun.com/weixin_44048021/article/details/123286993</guid><author>weixin_44048021</author><pubDate>Fri, 04 Mar 2022 22:52:54 +0800</pubDate><description><![CDATA[根据仿真结果可以知道，结果是完全相同的。

源代码：


module symbexam(
	//input 
	d1,
	d2,
	//output
	signed_out,
	unsigned_out
);
input	[3:0]	d1;
input 	[3:0]	d2;
output 	[4:0] 	unsigned_out;
output 	signed [4:0] 	signed_out;
//unsigned add;
assign unsigned_out = d1+d2;
//signed ]]></description><category></category></item><item><title><![CDATA[基于MATLAB的音频特征提取]]></title><link>https://blog.youkuaiyun.com/weixin_44048021/article/details/123262940</link><guid>https://blog.youkuaiyun.com/weixin_44048021/article/details/123262940</guid><author>weixin_44048021</author><pubDate>Thu, 03 Mar 2022 20:29:18 +0800</pubDate><description><![CDATA[音频文件无法上传。就只上传代码。



分帧：





分帧是指按照一定长度将输入的声音数据分割成若干数据段，通常取N=512个采样点作为一帧，帧与帧之间如果相互连接会使得在后续的计算中丢失数据，所以取256个采样点的一个帧移。

汉宁窗：







梅尔滤波器，取个数为64个：

















MFSC:








clc;
clear all;
close all;
%读取音频文件的第2-10s
fs = 16000;
[y,fs]=aud...]]></description><category></category></item><item><title><![CDATA[先调用PLL的IP核，再调用NCO的IP核时toolbench崩溃]]></title><link>https://blog.youkuaiyun.com/weixin_44048021/article/details/123248827</link><guid>https://blog.youkuaiyun.com/weixin_44048021/article/details/123248827</guid><author>weixin_44048021</author><pubDate>Thu, 03 Mar 2022 11:08:47 +0800</pubDate><description><![CDATA[创建NCO，fiR的IP核，这里点击next，弹出“loading ip toolbar”但是加载完这个并不弹出ip toolbench。返回创建文件夹的位置，发现错误



打开log文件，显示



应该不是license破解的问题，因为



像PLL等不需要toolbench的IP 核是可以使用的



，license里面也是包含了NCO，FIR等IP核

这个问题是在我先调用PLL的IP核，再调用NCO的IP核时出现的，在此之前，我试过仅调用NCOIP核，是可以调用的。但是现在这个问题...]]></description><category></category></item></channel></rss>