html中summary属性值为test,counter10_summary.html

Xilinx Design Summary

fdiv100hz Project Status
Project File:	miaobiao.xise	Parser Errors:	No Errors
Module Name:	counter10	Implementation State:	New
Target Device:	xc3s200a-5ft256	Errors:
Product Version:	ISE 13.4	Warnings:
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:		Final Timing Score:

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report
Map Report
Place and Route Report
Power Report
Post-PAR Static Timing Report
Bitgen Report

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 11/23/2017 - 10:35:34

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