LPC1225FBD64/301,1/SC16C752BIB48,157 托盘

高性能以太网MAC设计
本文介绍了一款高性能10/100Mbit/s以太网MAC的设计,该MAC通过DMA硬件加速提供优化的性能,并支持全双工和半双工操作、流控制等功能。此外,还详细介绍了其内存管理和PHY接口等特性。

7.8.1 Features

• Bit level set and clear registers allow a single instruction to set or clear any number of

bits in one port.

• Direction control of individual bits.

• All I/O default to inputs after reset.

• Backward compatibility with other earlier devices is maintained with legacy PORT0

and PORT1 registers appearing at the original addresses on the APB bus.

7.9 Ethernet

The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC

designed to provide optimized performance through the use of DMA hardware

acceleration. Features include a generous suite of control registers, half or full duplex

operation, flow control, control frames, hardware acceleration for transmit retry, receive

packet filtering and wake-up on LAN activity. Automatic frame transmission and reception

with Scatter-Gather DMA off-loads many operations from the CPU.

The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access

the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic

in the LPC2364/66/68 takes place on a different AHB subsystem, effectively separating

Ethernet activity from the rest of the system. The Ethernet DMA can also access the USB

SRAM if it is not being used by the USB block.

The Ethernet block interfaces between an off-chip Ethernet PHY using the RMII (reduced

MII) protocol and the on-chip MIIM (Media Independent Interface Management) serial

bus.

7.9.1 Features

• Ethernet standards support:

– Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,

100 Base-FX, and 100 Base-T4.

– Fully compliant with IEEE standard 802.3.

– Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back

pressure.

– Flexible transmit and receive frame options.

– VLAN frame support.

• Memory management:

– Independent transmit and receive buffers memory mapped to shared SRAM.

– DMA managers with scatter/gather DMA and arrays of frame descriptors.

– Memory traffic optimized by buffering and pre-fetching

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