signature=348a7ccbb9abe65fb90d6a0f44514435,Built-in self test for memory interconnect testing

转载于 2021-05-29 18:28:04 发布 · 106 阅读

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本文介绍了一种内置在集成电路(IC)中的自检逻辑(BIST)，它与内存控制器逻辑配合，用于在正常模式下通过驱动电路快速传输地址和命令信息，同时在测试模式下通过驱动电路进行芯片间的通信测试。BIST增强了设备的可靠性，确保了内存访问的准确性。

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摘要：

In some embodiments, built-in self-test logic is provided for an integrated circuit (IC) device having memory controller logic to generate address and command information for accessing a memory device. Driver circuits are on-chip with the memory controller logic. The driver circuits have outputs that are coupled to on-chip signal pads, respectively. The BIST logic is coupled between the driver circuits and the controller logic. The BIST logic is to transmit, at speed, address and command information that has been generated by the controller logic using the driver circuits in a normal mode of operation for the device. In addition, the BIST logic is able to transmit, at speed, test symbols using the driver circuits in a test mode of operation for the IC device, during which a chip-to-chip connection between the IC device and another device is tested. Other embodiments are also described and claimed.

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