Q146 - Q151 Exams/m2014 q6c / m2014 q6 / 2012 q2fsm / 2012 q2b / 2013 q2afsm / 2013 q2bfsm

题目都比较简单，就直接过一遍代码吧

Q146 Exams/m2014 q6c

题目链接：Exams/m2014 q6c - HDLBits (01xz.net)

代码如下：

module top_module (
    input [6:1] y,
    input w,
    output Y2,
    output Y4);
    
    
    assign  Y2 = y[1]&~w;
    assign	Y4 = (y[2]&w)||(y[3]&w)||(y[5]&w)||(y[6]&w);

endmodule

Q147 Exams/m2014 q6

题目链接：Exams/m2014 q6 - HDLBits (01xz.net)

锻炼一下自己，因此采用独热码状态机的写法，代码如下：

module top_module (
    input clk,
    input reset,     // synchronous reset
    input w,
    output z);
    
    parameter A = 6'b000001;
    parameter B = 6'b000010;
    parameter C = 6'b000100;
    parameter D = 6'b001000;
    parameter E = 6'b010000;
    parameter F = 6'b100000;
    
    parameter NUM_A = 0;
    parameter NUM_B = 1;
    parameter NUM_C = 2;
    parameter NUM_D = 3;
    parameter NUM_E = 4;
    parameter NUM_F = 5;
    
    reg	[5:0]	curr_state;
    reg	[5:0]	next_state;
    
    always @(posedge clk) begin
        if(reset) begin
           curr_state <= A; 
        end
        else begin
           curr_state <= next_state; 
        end
    end
    
    always @(*) begin
        case(1'b1)
            curr_state[NUM_A]:next_state = w ? A : B;
            curr_state[NUM_B]:next_state = w ? D : C;
            curr_state[NUM_C]:next_state = w ? D : E;
            curr_state[NUM_D]:next_state = w ? A : F;
            curr_state[NUM_E]:next_state = w ? D : E;
            curr_state[NUM_F]:next_state = w ? D : C;
            default:next_state = A;
        endcase
    end
    
    assign z = curr_state[NUM_E] || curr_state[NUM_F];
    

endmodule

Q148 Exams/2012 q2fsm

题目链接：Exams/2012 q2fsm - HDLBits (01xz.net)

 代码如下：

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    input w,
    output z
);
    
    parameter A = 6'b000001;
    parameter B = 6'b000010;
    parameter C = 6'b000100;
    parameter D = 6'b001000;
    parameter E = 6'b010000;
    parameter F = 6'b100000;
    
    parameter NUM_A = 0;
    parameter NUM_B = 1;
    parameter NUM_C = 2;
    parameter NUM_D = 3;
    parameter NUM_E = 4;
    parameter NUM_F = 5;
    
    reg	[5:0]	curr_state;
    reg	[5:0]	next_state;
    
    always @(posedge clk) begin
        if(reset) begin
           curr_state <= A; 
        end
        else begin
           curr_state <= next_state; 
        end
    end
    
    always @(*) begin
        case(1'b1)
            curr_state[NUM_A]:next_state = w ? B : A;
            curr_state[NUM_B]:next_state = w ? C : D;
            curr_state[NUM_C]:next_state = w ? E : D;
            curr_state[NUM_D]:next_state = w ? F : A;
            curr_state[NUM_E]:next_state = w ? E : D;
            curr_state[NUM_F]:next_state = w ? C : D;
            default:next_state = A;
        endcase
    end
    
    assign z = curr_state[NUM_E] || curr_state[NUM_F];
    

endmodule

Q149  Exams/2012 q2b

题目链接：Exams/2012 q2b - HDLBits (01xz.net)

代码如下：

module top_module (
    input [5:0] y,
    input w,
    output Y1,
    output Y3
);

    assign Y1 = y[0]&w;
    assign Y3 = (~w)&&(y[2]||y[1]||y[4]||y[5]);
    
    
endmodule

Q150 Exams/2013 q2afsm

题目链接：Exams/2013 q2afsm - HDLBits (01xz.net)

代码如下：

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input [3:1] r,   // request
    output [3:1] g   // grant
); 
    
    parameter A = 2'b00;
    parameter B = 2'b01;
    parameter C = 2'b10;
    parameter D = 2'b11;
    
    reg	[1:0]	curr_state;
    reg	[1:0]	next_state;
    
    always@(posedge clk ) begin
        if(~resetn) begin
           curr_state <= A; 
        end
        else begin
           curr_state <= next_state; 
        end
    end
    
    always @(*) begin
        case(curr_state)
            A:next_state = r[1]?B:r[2]?C:r[3]?D:A;
            B:next_state = r[1]?B:A;
            C:next_state = r[2]?C:A;
            D:next_state = r[3]?D:A;
            default:next_state = A;
        endcase
    end
    
    assign g[1] = (curr_state == B)?1'b1:1'b0;
    assign g[2] = (curr_state == C)?1'b1:1'b0;
    assign g[3] = (curr_state == D)?1'b1:1'b0;
    

endmodule

Q151 Exams/2013 q2bfsm

题目链接：Exams/2013 q2bfsm - HDLBits (01xz.net)

实际就是两个序列检测，使用摩尔型状态机的时候每个输出都需要有各自的状态，因此我们可以画出状态图如下

状态转移图：

代码如下：

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input x,
    input y,
    output f,
    output g
); 
    
    parameter A = 4'd0;
    parameter B = 4'd1;
    parameter C = 4'd2;
    parameter D = 4'd3;
    parameter E = 4'd4;
    parameter F = 4'd5;
    parameter G = 4'd6;
    parameter H = 4'd7;
    parameter I = 4'd8;

    reg [3:0] curr_state;
    reg	[3:0] next_state;
    
    always@(posedge clk) begin
        if(~resetn) begin
            curr_state <= A;
        end
        else begin
            curr_state <= next_state;
        end
    end
           
    always @(*) begin
        case(curr_state)
            A:next_state = B;
            B:next_state = C;
            C:next_state = x ? D : C;
            D:next_state = x ? D : E;
            E:next_state = x ? F : C;
            F:next_state = y ? G : H;
            G:next_state = G;
            H:next_state = y ? G : I;
            I:next_state = I;
            default:next_state = A;
        endcase  
    end
           
    assign f = (curr_state == B)?1'b1:1'b0; 
    assign g = ((curr_state == F)||(curr_state == G)||(curr_state == H))?1'b1:1'b0;

endmodule