Serval and Parenthesis Sequence

C. Serval and Parenthesis Sequence

time limit per test

1 second

memory limit per test

256 megabytes

input

standard input

output

standard output

Serval soon said goodbye to Japari kindergarten, and began his life in Japari Primary School.

In his favorite math class, the teacher taught him the following interesting definitions.

A parenthesis sequence is a string, containing only characters "(" and ")".

A correct parenthesis sequence is a parenthesis sequence that can be transformed into a correct arithmetic expression by inserting characters "1" and "+" between the original characters of the sequence. For example, parenthesis sequences "()()", "(())" are correct (the resulting expressions are: "(1+1)+(1+1)", "((1+1)+1)"), while ")(" and ")" are not. Note that the empty string is a correct parenthesis sequence by definition.

We define that |s||s| as the length of string ss. A strict prefix s[1…l]s[1…l] (1≤l<|s|)(1≤l<|s|) of a string s=s1s2…s|s|s=s1s2…s|s| is string s1s2…sls1s2…sl. Note that the empty string and the whole string are not strict prefixes of any string by the definition.

Having learned these definitions, he comes up with a new problem. He writes down a string ss containing only characters "(", ")" and "?". And what he is going to do, is to replace each of the "?" in ss independently by one of "(" and ")" to make all strict prefixes of the new sequence not a correct parenthesis sequence, while the new sequence should be a correct parenthesis sequence.

After all, he is just a primary school student so this problem is too hard for him to solve. As his best friend, can you help him to replace the question marks? If there are many solutions, any of them is acceptable.

Input

The first line contains a single integer |s||s| (1≤|s|≤3⋅1051≤|s|≤3⋅105), the length of the string.

The second line contains a string ss, containing only "(", ")" and "?".

Output

A single line contains a string representing the answer.

If there are many solutions, any of them is acceptable.

If there is no answer, print a single line containing ":(" (without the quotes).

Examples

input

Copy

6
(?????

output

Copy

(()())

input

Copy

10
(???(???(?

output

Copy

:(

Note

It can be proved that there is no solution for the second sample, so print ":(".

解题思路:

#include<iostream>
#include<cstdio>
#include<cstring>
#include<queue>
#include<vector>
#include<string>
#include<cmath>
#include<bitset>
#include<algorithm>
#include<map>
using namespace std;
#define LL long long
#define N 300005
#define maxn 200005
#define inf 0x3f3f3f3f
#define sca(x) scanf("%d",&x)
#define fir first
#define sec second
#define mp(x,y) make_pair(x,y)
#define pb(x) push_back(x)
#define N 105

int n;
int main()
{
    cin>>n;
    string s;
    cin>>s;
    int num1=0,num2=0;
    for(int i=0;i<n;i++){
        if(s[i]=='(')num1++;
        if(s[i]==')')num2++;
    }
    int sum=0;
    for(int i=0;i<n;i++){
        if(s[i]=='(')sum++;
        else if(s[i]==')')sum--;
        else
        {
            if(num1<n/2){
                s[i]='(';
                num1++;
                sum++;
            }else{
                s[i]=')';
                num2++;
                sum--;
            }
        }
        if(i!=n-1&&sum<=0){
            puts(":(");
            return 0;
        }
    }
    if(sum!=0)puts(":(");
    else
    cout<<s<<endl;
}
/*
要满足题意只需要保证两个条件即可,
每时每刻左括号数都大于右括号数,并且最终
左右括号各占一半。
*/

 

这个模块有自动眼图扫描吗,需不需要添加逻辑完成? // RX_BITSLICE : In order to incorporate this function into the design, // Verilog : the following instance declaration needs to be placed // instance : in the body of the design code. The instance name // declaration : (RX_BITSLICE_inst) and/or the port declarations within the // code : parenthesis may be changed to properly reference and // : connect this function to the design. All inputs // : and outputs must be connected. // <-----Cut code below this line----> // RX_BITSLICE: RX_BITSLICE for input using Native Mode // Kintex UltraScale // Xilinx HDL Language Template, version 2023.2 RX_BITSLICE #( .CASCADE("FALSE"), // Enables cascading of IDELAY and ODELAY lines .DATA_TYPE("DATA"), // Defines what the input pin is carrying (CLOCK, DATA, DATA_AND_CLOCK, // SERIAL) .DATA_WIDTH(8), // Defines the width of the serial-to-parallel converter (4-8) .DELAY_FORMAT("TIME"), // Units of the DELAY_VALUE (COUNT, TIME) .DELAY_TYPE("FIXED"), // Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD) .DELAY_VALUE(0), // Input delay value setting in ps .DELAY_VALUE_EXT(0), // Value of the extended input delay value in ps .FIFO_SYNC_MODE("FALSE"), // Always set to FALSE. TRUE is reserved for later use. .IS_CLK_EXT_INVERTED(1'b0), // Optional inversion for CLK_EXT .IS_CLK_INVERTED(1'b0), // Optional inversion for CLK .IS_RST_DLY_EXT_INVERTED(1'b0), // Optional inversion for RST_DLY_EXT .IS_RST_DLY_INVERTED(1'b0), // Optional inversion for RST_DLY .IS_RST_INVERTED(1'b0), // Optional inversion for RST .REFCLK_FREQUENCY(300.0), // Specification of the reference clock frequency in MHz (200.0-2667.0) .SIM_DEVICE("ULTRASCALE"), // Set the device version for simulation functionality (ULTRASCALE) .UPDATE_MODE("ASYNC"), // Determines when updates to the delay will take effect (ASYNC, MANUAL, // SYNC) .UPDATE_MODE_EXT("ASYNC") // Determines when updates to the extended input delay will take effect // (ASYNC, MANUAL, SYNC) ) RX_BITSLICE_inst ( .CNTVALUEOUT(CNTVALUEOUT), // 9-bit output: Counter value to device logic .CNTVALUEOUT_EXT(CNTVALUEOUT_EXT), // 9-bit output: Optional extended (cascaded delay) counter value // going to the device logic .FIFO_EMPTY(FIFO_EMPTY), // 1-bit output: FIFO empty flag .FIFO_WRCLK_OUT(FIFO_WRCLK_OUT), // 1-bit output: FIFO source synchronous write clock out to the device // logic (currently unsupported, do not connect) .Q(Q), // 8-bit output: Registered output data from FIFO .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT), // 40-bit output: Output bus to BITSLICE_CONTROL .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT), // 40-bit output: Output bus to BITSLICE_CONTROL .CE(CE), // 1-bit input: Clock enable for IDELAY .CE_EXT(CE_EXT), // 1-bit input: Optional extended (cascaded delay) clock enable .CLK(CLK), // 1-bit input: Clock used to sample LOAD, CE, INC .CLK_EXT(CLK_EXT), // 1-bit input: Optional extended (cascaded delay) clock .CNTVALUEIN(CNTVALUEIN), // 9-bit input: Counter value from device logic .CNTVALUEIN_EXT(CNTVALUEIN_EXT), // 9-bit input: Optional extended (cascaded delay) counter value from // device logic .DATAIN(DATAIN), // 1-bit input: Input signal from IBUF .EN_VTC(EN_VTC), // 1-bit input: Enable IDELAYCTRL to keep stable delay over VT .EN_VTC_EXT(EN_VTC_EXT), // 1-bit input: Optional extended (cascaded delay) to keep stable // delay over VT .FIFO_RD_CLK(FIFO_RD_CLK), // 1-bit input: FIFO read clock .FIFO_RD_EN(FIFO_RD_EN), // 1-bit input: FIFO read enable .INC(INC), // 1-bit input: Increment the current delay tap setting .INC_EXT(INC_EXT), // 1-bit input: Optional extended (cascaded delay) increments the // current delay tap setting .LOAD(LOAD), // 1-bit input: Load the CNTVALUEIN tap setting .LOAD_EXT(LOAD_EXT), // 1-bit input: Optional extended (cascaded delay) load the // CNTVALUEIN_EXT tap setting .RST(RST), // 1-bit input: Asynchronous assert, synchronous deassert for // RX_BITSLICE ISERDES .RST_DLY(RST_DLY), // 1-bit input: Reset the internal DELAY value to DELAY_VALUE .RST_DLY_EXT(RST_DLY_EXT), // 1-bit input: Optional extended (cascaded delay) reset delay to // DELAY_VALUE_EXT .RX_BIT_CTRL_IN(RX_BIT_CTRL_IN), // 40-bit input: Input bus from BITSLICE_CONTROL .TX_BIT_CTRL_IN(TX_BIT_CTRL_IN) // 40-bit input: Input bus from BITSLICE_CONTROL ); // End of RX_BITSLICE_inst instantiation
最新发布
08-01
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