linux 启动如何获取lpj参数,linux kernel lpj参数

CELF提交的patch引入了预设LPJ(Loops Per Jiffy),以减少Linux内核启动时校准loops_per_jiffy的时间。loops_per_jiffy用于计算微小延迟,它表示每jiffy的循环次数。该patch允许用户在启动时预设LPJ值,避免复杂的计算,从而提高系统性能。

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CELF- CE Linux Forum 在kernel提交了一个“Preset LPJ”的patch,这个patch可以通过预设LPJ来减少linux kernel启动过程中校正loops_per_jiffy所需花费的时间。

What is loops_per_jiffy?

按字面的意思就是每jiffy的循环次数,jiffy是kernel 的一次节拍时间(HZ=100,则表示10ms),循环次数则表示cpu的循环次数。loops_per_jiffy用于系统实现微小时间delay函数。如果我们知道了loops_per_jiffy,那么就能计算出10us大概需要的循环数为

cpu_loops = 10us * loops_per_jiffy * HZ / 1000000

那么只要cpu循环cpu_loops 指定的循环,就可以达到10us延迟的目的。

系统是通过让CPU空转一定的循环来实现udelay和mdelay的,由于用loops_per_jiffy估算CPU loops是有一定误差的,所以udelay(500) delay的时间可能和500us有一定误差。

What this patch do?

CELF这个patch,其实就是增加了一个kernel 参数,使得用户可以在kernel启动时预设lpj,无须复杂的计算。

### RV1126 EMMC Clock Frequency Configuration Method and Parameters For the RV1126 platform, configuring the EMMC clock frequency involves several key steps within the boot process to ensure optimal performance of the embedded multimedia card interface. The configuration typically occurs during system initialization or through specific register settings. The calibration of delays and setting up clocks are critical aspects that influence how peripherals like EMMC operate. In Linux-based systems similar configurations can be observed where a delay loop is calibrated based on timer frequencies as seen in early kernel messages such as "Calibrating delay loop (skipped), value calculated using timer frequency.. 199.98 BogoMIPS (lpj=399960)"[^1]. However, this message pertains more broadly to general timing mechanisms rather than directly to EMMC setup but illustrates the importance of accurate timekeeping for peripheral operations. Specifically for configuring EMMC clock frequency on platforms like RV1126: - **Clock Source Selection**: Choose an appropriate parent clock source from available options which could include PLL outputs among others. - **Frequency Division Settings**: Apply division factors via registers controlling the EMMC module's input clock path so it meets required specifications without exceeding maximum ratings specified by hardware documentation. A typical approach would involve modifying device tree files or bootloader scripts depending upon implementation specifics provided by manufacturers. For instance, adjusting properties related to `mmc` nodes might look something along these lines when expressed in DTS format: ```dts &mmc { pinctrl-names = "default"; pinctrl-0 = <&mmc_pins>; bus-width = <4>; /* Or other widths */ cd-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; status = "okay"; mmc-clk-sel = <&ccu CLK_EMMC>,<desired_frequency_in_khz>; }; ``` This snippet demonstrates specifying desired operational characteristics including selecting a suitable clock rate for the controller. Note actual values depend heavily on silicon revisions and intended use cases thus consulting official datasheets remains essential. --related questions-- 1. What considerations should one take into account while choosing between different clock sources for EMMC? 2. How does altering the EMMC clock impact data transfer rates and power consumption? 3. Can you provide examples of common pitfalls encountered during EMMC clock tuning processes? 4. Is there any difference in configuring SDIO versus eMMC interfaces regarding their clocking schemes?
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