testbench实例 vhdl_VHDL testbench 例子，包含向文件中写数据

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

use std.textio.all;

use ieee.std_logic_textio.all;

ENTITY DFFNTest IS

END DFFNTest;

ARCHITECTURE behavior OF DFFNTest IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT DFFN

GENERIC ( INIT : bit := '0');

PORT(

Q  : OUT  std_logic;

CLK  : IN  std_logic;

D : IN  std_logic

);

END COMPONENT;

--Inputs

signal CLK : std_logic := '0';

signal D : std_logic := '0';

--Outputs

signal Q : std_logic;

file fh_w:text;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: DFFN PORT MAP (

Q => Q,

CLK => CLK,

D => D

);

write_proc:process

variable buf_w : line;

begin

wait for 91 ns;

wrtData:LOOP

wait for 10 ns;

write(buf_w,CLK);

write(buf_w,string'("  "));

write(buf_w,D);

write(buf_w,string'("  "));

write(buf_w,Q);

writeline(fh_w,buf_w);

END LOOP wrtData;

end process;

-- Stimulus process

stim_proc: process

variable fstatus:FILE_OPEN_STATUS;

variable buf_wh:line;

variable i :integer :=0;

begin

file_open(fstatus,fh_w,"DFFNtb_out.vrf",write_mode);

write(buf_wh,string'("CLK D  Q"));

writeline(fh_w,buf_wh);

wait for 100 ns;

loop1: while(i<50) loop

wait for 10 ns;

CLK <= not CLK;

if((i rem 3) = 0) then

D <= not D;

end if;

i := i+1;

end loop loop1;

file_close(fh_w);

wait;

end process;

END;