flow_led

最新推荐文章于 2023-01-14 16:31:12 发布

guoyang0709

最新推荐文章于 2023-01-14 16:31:12 发布

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分类专栏： FPGA

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流水灯代码

module flow_led(
	 input				   sys_clk,//20Mhz
    input				   sys_rst_n,
   
	output	reg[4:0]	   led
   );	
	
reg[25:0]	counter;
parameter Time=26'd1000_0000;//20Mhz晶振,1秒20M脉冲,0.5秒10Mhz脉冲.

always @(posedge sys_clk or negedge sys_rst_n) begin
	if(!sys_rst_n)
		counter <= 26'd0;
	else if (counter < Time)
		counter <= counter + 1'b1;
	else 	
		counter <= 26'd0;
end

always @(posedge sys_clk or negedge sys_rst_n) begin
	if(!sys_rst_n)
		led <= 5'b11110;
	else if (counter == Time)
		led[4:0] <= {led[0],led[2:1]};
	else 	
		led <= led;
end

endmodule

测试文件代码

module td_flow_led;

	// Inputs
	reg sys_clk;
	reg sys_rst_n;

	// Outputs
	wire [4:0] led;
	parameter delaytime = 26'd10;

	// Instantiate the Unit Under Test (UUT)
	flow_led #(.Time(delaytime))uut(
		.sys_clk(sys_clk), 
		.sys_rst_n(sys_rst_n), 
		.led(led)
	);
	always #20 sys_clk=~sys_clk;
	initial begin
		// Initialize Inputs
		sys_clk = 0;
		sys_rst_n = 0;

		// Wait 100 ns for global reset to finish
		#20;
		sys_rst_n =1;
		#2000;
		sys_rst_n =0;
        
		// Add stimulus here

	end
      
endmodule

UCF文件

NET "led[4]" LOC = P12;
NET "led[3]" LOC = P13;
NET "led[2]" LOC = P15;
NET "led[1]" LOC = P16;
NET "led[0]" LOC = P20;
NET "sys_clk" LOC = P86;
NET "sys_rst_n" LOC = P82;