uvm_reg_sequence——寄存器模型（六）

最新推荐文章于 2025-05-03 17:15:39 发布

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最新推荐文章于 2025-05-03 17:15:39 发布

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原文链接：http://www.cnblogs.com/dpc525/p/8025221.html

本文介绍了UVM中的uvm_reg_sequence类，它是所有寄存器序列的基类，包含了模型、适配器和 sequencer。uvm_reg_sequence构成了一个小型的UVM系统，用于处理寄存器的前门访问，包括uvm_reg_item、序列器和适配器，负责寄存器事务到物理总线事务的转换。

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寄存器模型

uvm_reg_sequence是UVM自带所有register sequence 的基类。该类包含model, adapter, reg_seqr(uvm_sequencer). 感觉寄存器模型是个小的UVM系统。有自己uvm_reg_item, uvm_reg_sequence，reg_seqr, uvm_reg_adapter 是用来将寄存器的transaction 和 physical bus transaction之间的转化

//------------------------------------------------------------------------------
// TITLE: Register Sequence Classes
//------------------------------------------------------------------------------
//
// This section defines the base classes used for register stimulus generation.
//------------------------------------------------------------------------------

                                                              
//------------------------------------------------------------------------------
//
// CLASS: uvm_reg_sequence
//
// This class provides base functionality for both user-defined RegModel test
// sequences and "register translation sequences".
//
// - When used as a base for user-defined RegModel test sequences, this class
//   provides convenience methods for reading and writing registers and
//   memories. Users implement the body() method to interact directly with
//   the RegModel model (held in the <model> propert