以下代码实现的功能，代码中所有信号的在代码中起到什么作用，代码是否具有普适性
-------------------------------------------------------------------------
-- This confidential and proprietary software_information may be used --
-- only as authorized by a licensing agreement for OCAM Limited --
-- (c) COPYRIGHT 2017-2020 OCAM Limited --
-- ALL RIGHTS RESERVED --
-- The entire notice above must be reproduced on all authorizd copies --
-- and copies may be made to the extent permitted by a licensing --
-- agreement from OCAM Limited. --
-------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
------------------------------------------------------------------------------------------------------------------------
entity idream_axis_csc_96_64_module is
generic(ppc_byten :integer :=16;
axi_byten :integer :=12);
port(
reset : in std_logic;
clk_axi : in std_logic;
clk_o : in std_logic;
vs_in : in std_logic;
en_in : in std_logic;
Vheight : in std_logic_vector(15 downto 0);
row_size : in std_logic_vector(15 downto 0);
--for axis
m0_axis_tdata : in std_logic_vector(axi_byten*8-1 downto 0);
m0_axis_tlast : in std_logic;
m0_axis_tready : out std_logic;
m0_axis_tstrb : in std_logic_vector(axi_byten-1 downto 0);
m0_axis_tuser : in std_logic;
m0_axis_tvalid : in std_logic;
m1_axis_tdata : in std_logic_vector(axi_byten*8-1 downto 0);
m1_axis_tlast : in std_logic;
m1_axis_tready : out std_logic;
m1_axis_tstrb : in std_logic_vector(axi_byten-1 downto 0);
m1_axis_tuser : in std_logic;
m1_axis_tvalid : in std_logic;
--vp in
m_axis_tdata : out std_logic_vector(ppc_byten*8-1 downto 0);
m_axis_tlast : out std_logic;
m_axis_tready : in std_logic;
m_axis_tstrb : out std_logic_vector(ppc_byten-1 downto 0);
m_axis_tuser : out std_logic;
m_axis_tvalid : out std_logic
);
end entity;
architecture RTL of idream_axis_csc_96_64_module is
------------------------------------------------------------------------------------------------------------------
component idream_bitwidth_simple_module is
generic(bit_i :integer :=12;
bit_o :integer :=64;
par_i :integer :=16 ;--delay par_i+2 clks
par_o :integer :=3;
mux_i :integer :=192
);
port(
reset : in std_logic;
clk : in std_logic;
pv_in : in std_logic;
en_in : in std_logic;
data_in : in std_logic_vector(bit_i-1 downto 0);
--ddr_bus
pv_out : out std_logic;
en_out : out std_logic;
data_out : out std_logic_vector(bit_o-1 downto 0)
);
end component;
------------------------------------------------------------------------------------------------------------------
component idream_axis_csc_read_module is
generic(ppc_byten :integer :=8);
port(
reset : in std_logic;
vs_in : in std_logic;
write_size : in std_logic_vector(31 downto 0);
dbg_fsm : in std_logic_vector(3 downto 0);
--for axis
clk_o : in std_logic;
m_axis_tdata : out std_logic_vector(ppc_byten*8-1 downto 0);
m_axis_tlast : out std_logic;
m_axis_tready : in std_logic;
m_axis_tstrb : out std_logic_vector(ppc_byten-1 downto 0);
m_axis_tuser : out std_logic;
m_axis_tvalid : out std_logic;
--vp in
clk_i : in std_logic;
ram_wraddr : in std_logic_vector(15 downto 0);
ram_wrdata : in std_logic_vector(127 downto 0);
ram_wren : in std_logic;
ready_en : in std_logic;
busy_en : in std_logic;
read_size : out std_logic_vector(31 downto 0);
frame_size : in std_logic_vector(31 downto 0)
);
end component;
------------------------------------------------------------------------------------------------------------------
component ila_axis is
port(
clk : in std_logic;
probe0 : in std_logic_vector(127 downto 0);
probe1 : in std_logic_vector(35 downto 0);
probe2 : in std_logic_vector(0 downto 0);
probe3 : in std_logic_vector(0 downto 0);
probe4 : in std_logic_vector(0 downto 0);
probe5 : in std_logic_vector(0 downto 0)
);
end component;
---------------------------------------------------------------------------------------------------
component vio_aux is
port(
clk : in std_logic;
probe_out0 : out std_logic_vector(0 downto 0);
probe_out1 : out std_logic_vector(15 downto 0)
);
end component;
--------------------------------------------------------------------------------------------
constant idle_status : std_logic_vector(3 downto 0):=x"0";
constant start0_status : std_logic_vector(3 downto 0):=x"1";
constant trans0_status : std_logic_vector(3 downto 0):=x"2";
constant stop_status : std_logic_vector(3 downto 0):=x"3";
constant wait_status : std_logic_vector(3 downto 0):=x"4";
constant start1_status : std_logic_vector(3 downto 0):=x"5";
constant trans1_status : std_logic_vector(3 downto 0):=x"6";
signal transmit_FSM,next_FSM : std_logic_vector(3 downto 0):=x"0";
signal width_byte : std_logic_vector(15 downto 0):=x"0A08";--856*3
signal vs_delay,en_delay : std_logic_vector(3 downto 0):=(others=>'0');
signal one_shot,one_wren : std_logic_vector(1 downto 0):=(others=>'0');
signal axis0_tready,axis1_tready,busy_en,ready_en : std_logic:='0';
signal ram_wren,ram_wren_d,ram_wren_c,ram_wrlast,col_en : std_logic:='0';
signal ram_wraddr,col_cnt : std_logic_vector(15 downto 0):=(others=>'0');
signal ram_wrdata,ram_wrdata0,ram_wrdata1,one_wrdata0,one_wrdata1,dbg_data,ram_wrdata_d : std_logic_vector(axi_byten*8-1 downto 0):=(others=>'0');
signal ram_wrdata_c : std_logic_vector(127 downto 0):=(others=>'0');
signal sub_num : std_logic_vector(3 downto 0):=(others=>'0');
signal read_size,write_size,frame_size : std_logic_vector(31 downto 0):=(others=>'0');
--------------------------------------------------------------------------------------------
begin
m0_axis_tready <= axis0_tready;
m1_axis_tready <= axis1_tready;
width_byte <= row_size;
frame_size <= Vheight * width_byte;
ram_wrdata0 <= m0_axis_tdata(7+72 downto 0+72)&m0_axis_tdata(15+72 downto 8+72)&m0_axis_tdata(23+72 downto 16+72)& m0_axis_tdata(7+48 downto 0+48)&m0_axis_tdata(15+48 downto 8+48)&m0_axis_tdata(23+48 downto 16+48)& m0_axis_tdata(7+24 downto 0+24)&m0_axis_tdata(15+24 downto 8+24)&m0_axis_tdata(23+24 downto 16+24)& m0_axis_tdata(7 downto 0)&m0_axis_tdata(15 downto 8)&m0_axis_tdata(23 downto 16);
ram_wrdata1 <= m1_axis_tdata(7+72 downto 0+72)&m1_axis_tdata(15+72 downto 8+72)&m1_axis_tdata(23+72 downto 16+72)& m1_axis_tdata(7+48 downto 0+48)&m1_axis_tdata(15+48 downto 8+48)&m1_axis_tdata(23+48 downto 16+48)& m1_axis_tdata(7+24 downto 0+24)&m1_axis_tdata(15+24 downto 8+24)&m1_axis_tdata(23+24 downto 16+24)& m1_axis_tdata(7 downto 0)&m1_axis_tdata(15 downto 8)&m1_axis_tdata(23 downto 16);
------------------------------------------------------------------------------------------------------------------
--FSM
process(clk_axi,reset)
begin
if(reset='1') then
transmit_FSM <= idle_status;
elsif(clk_axi'event and clk_axi='1') then
case transmit_FSM is
when idle_status =>
if(vs_delay(2)='0' and vs_delay(3)='1') then
transmit_FSM <= start0_status;
else
null;
end if;
when start0_status =>
next_FSM <= start1_status;
if(m0_axis_tuser='0') then
transmit_FSM <= trans0_status;
else
null;
end if;
when start1_status =>
next_FSM <= trans1_status;
if(m1_axis_tuser='0') then
transmit_FSM <= trans1_status;
else
null;
end if;
when trans0_status =>
if(en_delay(2)='0' and en_delay(3)='1')or(m0_axis_tuser='1') then
transmit_FSM <= wait_status;
elsif(m0_axis_tlast='1' and axis0_tready='1') then
transmit_FSM <= next_FSM;
else
null;
end if;
when trans1_status =>
if(en_delay(2)='0' and en_delay(3)='1')or(m1_axis_tuser='1') then
transmit_FSM <= wait_status;
elsif(m1_axis_tlast='1' and axis1_tready='1') then
transmit_FSM <= trans0_status;
else
null;
end if;
when wait_status =>
if(m0_axis_tuser='1' and m1_axis_tuser='1') then
transmit_FSM <= stop_status;
else
null;
end if;
when stop_status =>
if(vs_delay(2)='1' and vs_delay(3)='0') then
transmit_FSM <= idle_status;
else
null;
end if;
when others =>
transmit_FSM <= idle_status;
end case;
else
null;
end if;
end process;
------------------------------------------------------------------------------------------------------------------
--data
process(clk_axi)
begin
if(clk_axi'event and clk_axi='1') then
case transmit_FSM is
when idle_status =>
axis0_tready <= '0';
axis1_tready <= '0';
one_wren <= "00";
busy_en <= '0';
when start0_status =>
busy_en <= '1';
one_shot(0) <= '0';
one_wren(0) <= one_shot(0);
axis0_tready <= m0_axis_tuser;
if(one_shot(0)='1') then
ram_wrdata <= one_wrdata0;
else
ram_wrdata <= ram_wrdata0;
end if;
when start1_status =>
one_shot(1) <= '0';
one_wren(1) <= one_shot(1);
axis1_tready <= m1_axis_tuser;
if(one_shot(1)='1') then
ram_wrdata <= one_wrdata1;
else
ram_wrdata <= ram_wrdata1;
end if;
when trans0_status =>
axis1_tready <= m0_axis_tlast and (not m1_axis_tuser) and axis0_tready;
ram_wrdata <= ram_wrdata0;
if(sub_num>=6)or(m0_axis_tlast='1' and axis0_tready='1') then
axis0_tready <= '0';
else
axis0_tready <= not m0_axis_tuser;
end if;
if(m0_axis_tuser='1' and m0_axis_tvalid='1' and axis0_tready='1') then
one_shot(0) <= '1';
else
null;
end if;
when trans1_status =>
axis0_tready <= m1_axis_tlast and (not m0_axis_tuser) and axis1_tready;
ram_wrdata <= ram_wrdata1;
if(sub_num>=6)or(m1_axis_tlast='1' and axis1_tready='1') then
axis1_tready <= '0';
else
axis1_tready <= not m1_axis_tuser;
end if;
if(m1_axis_tuser='1' and m1_axis_tvalid='1' and axis1_tready='1') then
one_shot(1) <= '1';
else
null;
end if;
when wait_status =>
axis0_tready <= not m0_axis_tuser;
axis1_tready <= not m1_axis_tuser;
if(m0_axis_tuser='1' and m0_axis_tvalid='1' and axis0_tready='1') then
one_shot(0) <= '1';
else
null;
end if;
if(m1_axis_tuser='1' and m1_axis_tvalid='1' and axis1_tready='1') then
one_shot(1) <= '1';
else
null;
end if;
when stop_status =>
axis0_tready <= '0';
axis1_tready <= '0';
when others =>
null;
end case;
else
null;
end if;
end process;
------------------------------------------------------------------------------------------------------------------
process(clk_axi)
begin
if(clk_axi'event and clk_axi='1') then
vs_delay <= vs_delay(2 downto 0)&vs_in;
en_delay <= en_delay(2 downto 0)&en_in;
if((transmit_FSM=trans0_status or transmit_FSM=wait_status)and m0_axis_tuser='1' and m0_axis_tvalid='1' and axis0_tready='1')or((transmit_FSM=trans1_status or transmit_FSM=wait_status) and m1_axis_tuser='1' and m1_axis_tvalid='1' and axis1_tready='1') then
ram_wren <= '0';
else
ram_wren <= ((m0_axis_tvalid and axis0_tready) or one_wren(0))or((m1_axis_tvalid and axis1_tready) or one_wren(1));
end if;
ram_wrlast <= (m0_axis_tlast and axis0_tready and m0_axis_tvalid)or(m1_axis_tlast and axis1_tready and m1_axis_tvalid);
if(busy_en='0')or(ram_wrlast='1') then
col_cnt <= (others=>'0');
elsif(ram_wren='1') then
col_cnt <= col_cnt + conv_std_logic_vector(axi_byten,8);
else
null;
end if;
if(busy_en='0')or(ram_wrlast='1') then
col_en <= '1';
elsif(col_cnt>=width_byte-axi_byten and ram_wren='1') then
col_en <= '0';
else
null;
end if;
if(m0_axis_tvalid='1' and axis0_tready='1') then
one_wrdata0 <= ram_wrdata0;
else
null;
end if;
if(m1_axis_tvalid='1' and axis1_tready='1') then
one_wrdata1 <= ram_wrdata1;
else
null;
end if;
if(busy_en='0') then
ram_wraddr <= (others=>'0');
elsif(ram_wren_c='1') then
ram_wraddr <= ram_wraddr +'1';
else
null;
end if;
if(busy_en='0') then
write_size <= (others=>'0');
elsif(ram_wren='1' and col_en='1') then
write_size <= write_size + conv_std_logic_vector(axi_byten,8);
else
null;
end if;
if(busy_en='0') then
for i in 0 to axi_byten/2-1 loop
dbg_data(16*i+15 downto 16*i) <= conv_std_logic_vector(i,16);
end loop;
elsif(ram_wren_d='1') then
for i in 0 to axi_byten/2-1 loop
dbg_data(16*i+15 downto 16*i) <= dbg_data(16*i+15 downto 16*i) + conv_std_logic_vector(axi_byten/2,8);
end loop;
else
null;
end if;
sub_num <= write_size(13 downto 10) - read_size(13 downto 10);--when (32/8)*byte_n*512/8=1024,set 13 downto 10
if(sub_num>1)or(write_size>=frame_size)or(transmit_FSM=wait_status) then
ready_en <= busy_en;
else
ready_en <= '0';
end if;
ram_wren_d <= ram_wren and col_en;
ram_wrdata_d <= ram_wrdata;
else
null;
end if;
end process;
------------------------------------------------------------------------------------------------------------------
--uila_axis : ila_axis
-- port map(
-- clk => clk_axi ,
-- probe0 => ram_wrdata_c ,
-- probe1 => write_size(26 downto 0) & transmit_FSM & ram_wren_c & col_en & en_in & ram_wren & m_axis_err,
-- probe2(0) => axis0_tready ,
-- probe3(0) => m0_axis_tlast ,
-- probe4(0) => m0_axis_tuser ,
-- probe5(0) => m0_axis_tvalid
-- );
------------------------------------------------------------------------------------------------------------------
uidream_bitwidth_simple_module : idream_bitwidth_simple_module
generic map(bit_i => 96 ,
bit_o => 128 ,
par_i => 4 ,--delay par_i+2 clks
par_o => 3 ,
mux_i => 384 )
port map(
reset => reset ,
clk => clk_axi ,
pv_in => ram_wren_d ,
en_in => busy_en ,
data_in => ram_wrdata_d ,--dbg_data ram_wrdata_d
--ddr_bus
pv_out => ram_wren_c ,
en_out => open ,
data_out => ram_wrdata_c
);
------------------------------------------------------------------------------------------------------------------
uidream_axis_csc_read_module : idream_axis_csc_read_module
generic map(ppc_byten => ppc_byten)
port map(
reset => reset ,
vs_in => vs_in ,
write_size => write_size ,
dbg_fsm => transmit_FSM ,
--for axis
clk_o => clk_o ,
m_axis_tdata => m_axis_tdata ,
m_axis_tlast => m_axis_tlast ,
m_axis_tready => m_axis_tready ,
m_axis_tstrb => m_axis_tstrb ,
m_axis_tuser => m_axis_tuser ,
m_axis_tvalid => m_axis_tvalid ,
--vp in
clk_i => clk_axi ,
ram_wraddr => ram_wraddr ,
ram_wrdata => ram_wrdata_c ,
ram_wren => ram_wren_c ,
ready_en => ready_en ,
busy_en => busy_en ,
read_size => read_size ,
frame_size => frame_size
);
-----------------------------------------------------------------------------------------------------------------
end RTL;
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