流水灯实验

最新推荐文章于 2018-12-11 21:52:58 发布

转载最新推荐文章于 2018-12-11 21:52:58 发布 · 150 阅读

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CC 4.0 BY-SA版权

原文链接：http://www.cnblogs.com/fengyanlover/p/5021200.html

本文介绍了一种使用Verilog HDL语言实现流水灯控制的方法。通过定时器控制LED灯以1秒间隔从左至右流动，展示了如何利用计数器实现精确的时间控制，并详细解释了信号传递过程。

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开发板上有一排LED灯，共26个，LEDR17-LEDR0-LEDG7-LEDG0;

实现以1s间隔从左至右流，循环不断~

完整代码如下（用的依旧是自动生成的模板）：

//=======================================================
//  This code is generated by Terasic System Builder
//=======================================================

module LED_Test(
    //////////// CLOCK //////////
    CLOCK_50,
    RSTn,
    //////////// LED //////////
    LEDG,
    LEDR 
);
//=======================================================
//  PORT declarations
//=======================================================

//////////// CLOCK //////////
input                          CLOCK_50;
input                            RSTn;
//////////// LED //////////
output             [8:0]        LEDG;
output            [17:0]        LEDR;

//=======================================================
//  Structural coding
//=======================================================

//-----------------------定时器模板--------------------------
//----1MS定时器
parameter T1MS = 16'd49_999;
reg    [15:0]    Count1;
always@(posedge CLOCK_50 or negedge RSTn)
    if(!RSTn)
        Count1 <= 16'd0;
    else if(Count1 == T1MS)
        Count1 <= 16'd0;
    else
        Count1 <= Count1 + 1'b1;        
        
//----1S定时器
reg    [9:0]    Count_MS;
always@(posedge CLOCK_50 or negedge RSTn)
    if(!RSTn)
        Count_MS <= 10'd0;
    else if(Count_MS == 16'd1000)
        Count_MS <= 10'd0;
    else if(Count1 == T1MS)
        Count_MS <= Count_MS + 1'b1;
  
//----------------------------------------------------------
//---------------------流水灯实现---------------------------
reg    [26:0]    rLED;

always@(posedge CLOCK_50 or negedge RSTn)
    if(!RSTn)
        rLED <= 27'b1000_0000_0000_0000_0000_0000_00;
    else if(Count_MS == 16'd1000)
        begin
            if(rLED == 27'b0000_0000_0000_0000_0000_0000_001)    //首尾交接处
                rLED <= 27'b1000_0000_0000_0000_0000_0000_000;
            else if(rLED == 27'b0000_0000_0000_0000_0100_0000_000)   //红绿LED交接处
                rLED <= 27'b0000_0000_0000_0000_0001_0000_000;
            else
                rLED <= {1'b0,rLED[26:1]};
        end

//-----------------------------------------------------------------

// 输出赋值
assign LEDR = rLED[26:9];
assign LEDG = {1'b0,rLED[7:0]};  //由于LEDG8跟它们一排LED不在同一排，所以就分出来置零好了


endmodule

转载于:https://www.cnblogs.com/fengyanlover/p/5021200.html