error : uvm_component_utils is undefined

最新推荐文章于 2025-05-17 11:04:21 发布

转载最新推荐文章于 2025-05-17 11:04:21 发布 · 807 阅读

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原文链接：http://www.cnblogs.com/testset/p/3426975.html

本文解决了一个关于UVM宏在Verilog文件中未被正确包含而导致的一系列编译错误问题。错误涉及宏定义缺失、变量未定义及语法错误等。通过确保`uvm_macros.svh`被正确引入到顶层文件中解决了这些问题。

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the simple reason is the uvm_macros.svh not included in the top file

and note: there is no need to add +incdir+ to look for the svh

because the questa will automatically fix the path when import uvm_pkg

** Error: Environment.sv(16): (qverilog-2163) Macro `uvm_component_utils is undefined.

** Error: Environment.sv(16): near "(": syntax error, unexpected '(', expecting function or task
** Error: Environment.sv(19): near "new": syntax error, unexpected new, expecting TYPE_IDENTIFIER
** Error: Environment.sv(24): near "build": syntax error, unexpected IDENTIFIER, expecting TYPE_IDENTIFIER
** Error: Environment.sv(30): near "endfunction": syntax error, unexpected endfunction
** Error: Environment.sv(33): near "connect": syntax error, unexpected IDENTIFIER, expecting TYPE_IDENTIFIER
** Error: Environment.sv(37): near "endfunction": syntax error, unexpected endfunction
** Error: test.sv(12): (qverilog-2163) Macro `uvm_component_utils is undefined.
** Error: test.sv(19): (qverilog-2730) Undefined variable: 't_env'.
** Error: test.sv(22): near "task": syntax error, unexpected task, expecting IDENTIFIER or TYPE_IDENTIFIER
** Error: test.sv(25): near "endtask": syntax error, unexpected endtask
** Error: top.sv(33): (qverilog-2730) Undefined variable: 'Clock'.

转载于:https://www.cnblogs.com/testset/p/3426975.html