微型计算机程序代码比较大小,《微型计算机原理及应用技术》程序代码.doc

《微型计算机原理及应用技术》程序代码

《微型计算机原理及应用技术》编程程序

目录：

2分频电路

N分频电路(8选一为例)

多进制加法计数器

基本D触发器

数据选择器(四选一)

异步复位可逆计数器

优先编码器

2分频电路

library ieee;

use ieee.std_logic_1164.all;

entity fredvider1 is

port(

clock:in std_logic;

clkout:out std_logic

);

end;

architecture behavior of fredvider1 is

signal clk:std_logic;

begin

process(clock)

begin

if rising_edge(clock) then

clk<=not clk;

end if;

end process;

clkout<=clk;

end;

N分频电路(8选一为例)

library ieee;

use ieee.std_logic_1164.all;

entity fredevider8 is

port

(clkin:in std_logic;

clkout:out std_logic);

end;

architecture bhv of fredevider8 is

constant n:integer:=3;

signal counter:integer range 0 to N;

signal clk:std_logic;

begin

process(clkin)

begin

if rising_edge(clkin) then

if counter = n then

counter <=0;

clk <= not clk;

else

counter <= counter+1;

end if;

end if;

end process;

clkout <= clk;

end;

多进制加法计数器

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity count2 is

port

(cp,res:in std_logic;

ql,qh:out std_logic_vector(3 downto 0));

end;

architecture bhv of count2 is

signal qnl,qnh:std_logic_vector(3 downto 0);

begin

process(cp,res)

begin

if res = '1' then qnl<="0000";qnh<="0000";

elsif rising_edge(cp) then

if qnl="0011" and qnh="0010"

then qnl<="0000";

qnh<="0000";

elsif qnl="1001" then qnl<="0000";qnh<=qnh+1;

else qnl<=qnl+1;

end if;

end if;

end process;

ql <= qnl;

qh <= qnh;

end;

基本D触发器

library ieee;

use ieee.std_logic_1164.all;

entity dff1 is

port( d: in std_logic;

clk: in std_logic;

q: out std_logic);

end;

architecture bhv of dff1 is

signal qn: std_logic;

begin

process(clk)

begin

if rising_edge(clk) then

qn<=d;

end if;

end process;

q<= qn;

end;

异步复位的D触发器

library ieee;

use ieee.std_logic_1164.all;

entity dff2 is

port(D,clk,clr: in std_logic;

Q: out std_logic);

――定义输入、输出端口

end entity dff2;

architecture one of dff2 is

begin

process(clk,D,clr)