B. A and B and Compilation Errors

本文分享了解决Codeforces B题的优化算法,通过排序和比较,避免了原始的暴力解法中可能出现的超时问题,提高了算法效率。

题目链接:http://codeforces.com/contest/519/problem/B

 

这道题目有点像求两个集合的差集

 

一开始就是单纯的去想用短的那个集合去和大的集合去比较,算法也没有想着去优化

结果就超时了

超时代码也贴出来把hhhh

#include <cstdio>
#include <cstring>
#include <iostream>
#include <cstdbool>

using namespace std;




int main()
{
    int n;
    scanf("%d",&n);
    int a[n],b[n-1],c[n-2];
    for (int i=0;i<n;i++)
    {
        scanf("%d",&a[i]);
    }
    for (int i=0;i<n-1;i++)
    {
        scanf("%d",&b[i]);
    }
    for (int i=0;i<n-2;i++)
    {
        scanf("%d",&c[i]);
    }
    for (int i=0;i<n-1;i++)
    {
        for (int j=0;j<n;j++)
        {
            if (b[i] == a[j])
            {
                a[j] = 0;
                break;
            }
        }
    }
    for (int i=0;i<n;i++)
    {
        if (a[i] != 0)
        {
            printf("%d\n",a[i]);
        }
    }
    for (int i=0;i<n-2;i++)
    {
        for (int j=0;j<n-1;j++)
        {
            if (c[i] == b[j])
            {
                b[j] = 0;
                break;
            }
        }
    }
    for (int i=0;i<n-1;i++)
    {
        if (b[i] != 0)
        {
            printf("%d",b[i]);
        }
    }
    return 0;
}

 

非常暴力的解法hh

 

后来想着去优化,就是先对集合元素排序,然后再进行比较。这样就可以减少算法的复杂度,不会出现n*n的复杂度

如果出现一个不匹配我们直接把它数出来就可以。

如果遍历到底也没出现不匹配的,就说明长集合的最后一个是不匹配的!(这算是一个特例吧,我们就进行一个特判)

 

AC代码:

#include <cstdio>
#include <cstring>
#include <iostream>
#include <algorithm>
#include <cstdbool>

using namespace std;




int main()
{
    int n;
    scanf("%d",&n);
    int a[n],b[n-1],c[n-2];
    for (int i=0;i<n;i++)
    {
        scanf("%d",&a[i]);
    }
    for (int i=0;i<n-1;i++)
    {
        scanf("%d",&b[i]);
    }
    for (int i=0;i<n-2;i++)
    {
        scanf("%d",&c[i]);
    }
    sort(a,a+n);
    sort(b,b+n-1);
    sort(c,c+n-2);
    int p = 0;
    int l = 0;
    int i;
    for (i=0;i<n-1;i++)
    {
        p++;
        if (a[i] != b[i])
        {
            printf("%d\n",a[i]);
            break;
        }
    }
    if (p == i)
    {
        printf("%d\n",a[p]);
    }
    for (i=0;i<n-2;i++)
    {
        l++;
        if (b[i] != c[i])
        {
            printf("%d\n",b[i]);
            break;
        }
    }
    if (l == i)
    {
        printf("%d\n",b[l]);
    }
    return 0;

}

 

转载于:https://www.cnblogs.com/-Ackerman/p/11091345.html

Error (10170): Verilog HDL syntax error at top.v(86) near text: "@"; expecting ".", or "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10170): Verilog HDL syntax error at top.v(94) near text: "@"; expecting ".", or "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10170): Verilog HDL syntax error at top.v(102) near text: "@"; expecting ".", or "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10170): Verilog HDL syntax error at top.v(110) near text: "@"; expecting ".", or "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10112): Ignored design unit "freq_div" at top.v(72) due to previous errors Error (10170): Verilog HDL syntax error at top.v(132) near text: "@"; expecting ".", or "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10170): Verilog HDL syntax error at top.v(162) near text: "begin"; expecting ".", or "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10112): Ignored design unit "top_clock" at top.v(117) due to previous errors Error (10170): Verilog HDL syntax error at top.v(189) near text: "@"; expecting ".", or "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10170): Verilog HDL syntax error at top.v(196) near text: "begin"; expecting ".", or "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10170): Verilog HDL syntax error at top.v(243) near text: "="; expecting ".", or an identifier. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10112): Ignored design unit "disp_scan" at top.v(172) due to previous errors Error (10170): Verilog HDL syntax error at top.v(256) near text: "{"; expecting ".", or "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10170): Verilog HDL syntax error at top.v(259) near text: "@"; expecting ".", or "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10149): Verilog HDL Declaration error at top.v(269): identifier "ALARM" is already declared in the present scope Error (10112): Ignored design unit "NowTime" at top.v(246) due to previous errors Info (12021): Found 0 design units, including 0 entities, in source file top.v Error: Quartus Prime Analysis & Synthesis was unsuccessful. 16 errors, 1 warning Error: Peak virtual memory: 4708 megabytes Error: Processing ended: Sun Jun 08 17:18:14 2025 Error: Elapsed time: 00:00:13 Error: Total CPU time (on all processors): 00:00:27 Error (293001): Quartus Prime Full Compilation was unsuccessful. 18 errors, 1 warning 你的代码有错,改一下再发我
06-09
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