2013-10-29 11:42:18
AR# 98753.1i XST - "WARNING: (FCT__0300). Model 'module_name' has different characteristics in destination library"
问题描述:新建一个新的工程文件 and2 ,这个文件名与xilinx的原语是有冲突的,所以不能作为model的name
官方解释为:
Description
Urgency: Standard
General Description:
If a user module/component (black box or functional) and a Xilinx primitive have the same name, the XST mapper will rename the user module/component.
Example:
"xor4" will be renamed to "xor41."
The warning messages from XST are:
WARNING: (FCT__0300). Model 'xor4' has different characteristics in destination library
WARNING: (FCT__0301). Model name has been changed to 'xor41'
Although Verilog is case-sensitive, this occurs for both VHDL and Verilog Synthesis, regardless of case.
Solution
C:\Xilinx\verilog\src\iSE\unisim_comp.v
C:\Xilinx\vhdl\src\unisims\unisim_VCOMP.vhd
NOTE: This issue is fixed in the 4.1i software release.