CPU特性标志及含义

flag	meaning
3DNOW	由AMD开发的一套SIMD多媒体指令集
3DNOWEXT	3DNOW Extended. Also known as AMD’s 3DNow!Enhanced 3DNow!Extensions
APIC	Advanced Programmable Interrupt Controller
CLFSH/CLFlush	Cache Line Flush
CMOV	Conditional Move/Compare Instruction
CMP_Legacy	Register showing the CPU is not Hyper-Threading capable
Constant_TSC	on Intel P-4s, the TSC runs with constant frequency independent of cpu frequency when EST is used
CR8Legacy	-unknown-
CX8	CMPXCHG8B Instruction. (Compare and exchange 8 bytes. Also known as F00F, which is an abbreviation of the hexadecimal encoding of an instruction that exhibits a design flaw in the majority of older Intel Pentium CPU).
CX16	CMPXCHG16B Instruction. (CMPXCHG16B allows for atomic operations on 128-bit double quadword (or oword) data types. This is useful for high resolution counters that could be updated by multiple processors (or cores). Without CMPXCHG16B the only way to perform such an operation is by using a critical section.)
DE	Debugging Extensions
DS	Debug Store
DS_CPL	CPL qualified Debug Store (whatever CPL might mean in this context)
DTS	Could mean Debug Trace Store or Digital Thermal Sensor, depending on source
EIST/EST	Enhanced Intel SpeedsTep
FXSR	FXSAVE/FXRSTOR. (The FXSAVE instruction writes the current state of the x87 FPU, MMX technology, Streaming SIMD Extensions, and Streaming SIMD Extensions 2 data, control, and status registers to the destination operand. The destination is a 512-byte memory location. FXRSTOR will restore the state saves).
FXSR_OPT	-unknown-
HT	Hyper-Transport. Note that the same abbreviation might is also used to indicate Hyper Threading (see below)
HTT/HT	Hyper-Threading. An Intel technology that allows quasi-parallel execution of different instructions on a single core. The single core is seen by applications as if it were two (or potentially more) cores. However, two true CPU cores are almost always faster than a single core with HyperThreading. This flag indicates support in the CPU when checking the flags in /proc/cpuinfo on Linux systems. For more info how you can detect active HyperThreading, see the first comment in my blog post about this page at [2]
HVM	Hardware support for virtual machines (Xen abbreviation for AMD SVM / Intel VMX)
LAHF_LM	Load Flags into AH Register, Long Mode.
LM	Long Mode. (64bit Extensions, AMD’s AMD64 or Intel’s EM64T).
MCA	Machine Check Architecture
MCE	Machine Check Exception
MMX	It is rumoured to stand for MultiMedia eXtension or Multiple Math or Matrix Math eXtension, but officially it is a meaningless acronym trademarked by Intel
MMXEXT	MMX Extensions – an enhanced set of instructions compared to MMX
MON/MONITOR	CPU Monitor
MSR	RDMSR and WRMSR Support
MTRR	Memory Type Range Register
NX	No eXecute, a flag that can be set on memory pages to disable execution of code in these pages
PAE	Physical Address Extensions. PAE is the added ability of the IA32 processor to address more than 4 GB of physical memory using Intel’s 36bit page addresses instead of the standard 32bit page addresses to access a total of 64GB of RAM. Also supported by many AMD chips
PAT	Page Attribute Table
PBE	Pending Break Encoding
PGE	PTE Global Bit
PNI	Prescott New Instruction. This was the codename for SSE3 before it was released on the Intel Prescott processor (which was later added to the Pentium 4 family name).
PSE	Page Size Extensions. (See PSE36)
PSE36	Page Size Extensions 36. IA-32 supports two methods to access memory above 4 GB (32 bits), PSE and PAE. PSE is the older and far less used version. For more information, take a look at [1].
SEP	SYSENTER and SYSEXIT
SS	Self-Snoop
SSE	Streaming SIMD Extensions. Developed by Intel for its Pentium III but also implemented by AMD processors from Athlon XP onwards
SSE2	Streaming SIMD Extensions 2. (An additional 144 SIMDs.) Introduced by Intel Pentium 4, on AMD since Athlon 64
SSE3	Streaming SIMD Extensions 3. (An additional 13 instructions) introduced with “Prescott” revision Intel Pentium 4 processors. AMD introduced SSE3 with the Athlon 64 “Venice” revision
SSSE3	Supplemental Streaming SIMD Extension 3. (SSSE3 contains 16 new discrete instructions over SSE3.) Introduced on Intel Core 2 Duo processors. No AMD chip supports SSSE3 yet.
SSE4	Streaming SIMD Extentions 4. Future Intel SSE revision adding 50 new instructions which will debut on Intel’s upcoming “Nehalem” processor in 2008. Also known as “Nehalem New Instructions (NNI)”
SVM	Secure Virtual Machine. (AMD’s virtualization extensions to the 64-bit x86 architecture, equivalent to Intel’s VMX, both also known as HVM in the Xen hypervisor.)
TM	Thermal Monitor
TM2	Thermal Monitor 2
TSC	Time Stamp Counter
VME	Virtual-8086 Mode Enhancement
VMX	Intel’s equivalent to AMD’s SVM
XTPR	TPR register chipset update control messenger. Part of the APIC code

转载于:https://www.cnblogs.com/allegro/archive/2012/08/22/2650976.html