VHDL中使用record type的使用

Record type的定义类似于C/C++中的结构的定义,tpye中可以包含其它已经定义的type.

 

在此贴出一个package文件,

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package chan_pkg is

constant c_WORDS : integer := 2;
constant c_32BITS_DATA : std_logic_vector := "01";
constant c_64BITS_DATA : std_logic_vector := "11";

type X_chan_t is record
Data : std_logic_vector(32*c_WORDS-1 downto 0); -- Data bus
ValidWords : std_logic_vector(c_WORDS-1 downto 0); -- indicates what are the valid 32-bits words on the data bus
Write : std_logic; -- Write command
end record;

type Y_chan_t is record
Ready : std_logic;
end record;

type X_chan_t_vector is array (natural range<>) of X_chan_t;
type Y_chan_t_vector is array (natural range<>) of Y_chan_t;

-- constants for inactive channels. Not ready, no data written.
constant c_DEFAULT_CHANNEL_X : X_chan_t := ((others=>'0'), (others=>'0'), '0');
constant c_DEFAULT_CHANNEL_Y : Y_chan_t := (ready=>'0');

end chan_pkg;

package body chan_pkg is

end package body chan_pkg;

 

其它VHDL文件要使用这些record文件,只需要包含这个package文件则可.

for example:

library xxx

use xxx.chan_pkg.all

 

entity yyy is

    (

        x_chan_in_0    :  IN  X_chan_t;

        y_chan_in_0    :  OUT Y_chan_t;

        x_chan_out_0 :  OUT  X_chan_t;

        y_chan_out_0 :   IN    Y_chan_t;

        clk                 :   in  std_logic;

        rst                :   in   std_logic;

        ce                 :   in   std_logic;

       ce_clr             :   in   std_logic

     );

end yyy;

具体信号的使用：  x_chan_out_0   <=  x_chan_in_0;

                        y_chan_in_0      <=  y_chan_out_0;

或者：

                      x_chan_out_0.data <= ........;

                     x_chan_out_0.write <= .........; 其它几个信号的操作则是类似.

 

更多关于Record type的定义和使用可参见： http://vhdl.renerta.com/source/vhd00055.htm

Made by Tim.

转载于:https://www.cnblogs.com/sundance/archive/2012/08/13/2636584.html