附录：ARM 手册 词汇表

来自：《DDI0406C_C_arm_architecture_reference_manual.pdf》p2723

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 能够查询到：“RAZ RAO WI 等的意思”

 

RAZ：Read-As-Zero 读到的总是0

RAO：Read-As-Oned读到的总是1

WI　：Writes Ignoredx 写无效

SBZP：Should-Be-Zero-or-Preserved on writes 写总是0

SBOP ： Should-Be-One-or-Preserved on writes. 写总是1

UNK：unknown 读写时返回值未知

 
Abort
An exception caused by an illegal memory access. Aborts can be caused by the external memory system or the MMU or MPU.


Addressing mode
Means a method for generating the memory address used by a load/store instruction.


Advanced SIMD
An extension to the ARM architecture that provides SIMD operations on a bank of extension registers. If the Floating-point extension is also implemented, the two extensions share the register bank and the Advanced SIMD operations include single-precision floating-point SIMD operations.


Aligned
A data item stored at an address that is divisible by the highest power of 2 that divides into its size in bytes. Aligned halfwords, words and doublewords therefore have addresses that are divisible by 2, 4 and 8 respectively.
An aligned access is one where the address of the access is aligned to the size of each element of the access.


Architecturally executed
An instruction is architecturally executed only if it would be executed in a simple sequential execution of the program. When such an instruction has been executed and retired is has been architecturally executed. Any instruction that, in a simple sequential execution of a program, is treated as a NOP because it fails its condition code check, is an architecturally executed instruction.

In a processor that performs speculative execution, an instruction is not  architecturally executed if the processor discards the results of a speculative execution.

ARM core registers
The ARM core registers comprise:
• thirteen general-purpose registers, R0 to R12, that software can use for processing
• SP, the stack pointer, that can also be referred to as R13
• LR, the link register, that can also be referred to as R14
• PC, the program counter, that can also be referred to as R15.

In some situations, software can use SP, LR, and PC for processing. The instruction descriptions include any constraints on the use of SP, LR, and PC.
See also High registers.


ARM instruction
A word that specifies an operation for a processor in ARM state to perform. ARM instructions must be word-aligned.


Associativity
See Cache associativity.


Atomicity
Describes either single-copy atomicity or multi-copy atomicity. Atomicity in the ARM architecture on page A3-128 defines these forms of atomicity for the ARM architecture.
See also Multi-copy atomicity, Single-copy atomicity.


Banked register
A register that has multiple instances, with the instance that is in use depending on the processor mode, security state, or other processor state.


Base register
A register specified by a load/store instruction that is used as the base value for the address calculation for the instruction. Depending on the instruction and its addressing mode, an offset can be added to or subtracted from the base register value to form the virtual address that is sent to memory.


Base register writeback
Describes writing back a modified value to the base register used in an address calculation.


Big-endian memory
Means that:
• a byte or halfword at a word-aligned address is the most significant byte or halfword in the word at that address
• a byte at a halfword-aligned address is the most significant byte in the halfword at that address.


Blocking
Describes an operation that does not permit following instructions to be executed before the operation completes.

A non-blocking operation can permit following instructions to be executed before the operation completes, and in the event of encountering an exception does not signal an exception to the processor. This enables implementations to retire following instructions while the non-blocking operation is executing, without the need to retain precise processor state.


Branch prediction
Is where a processor selects a future execution path to fetch along. For example, after a branch instruction, the processor can choose to speculatively fetch either the instruction following the branch or the instruction at the branch target.
See also Prefetching.


Breakpoint
A debug event triggered by the execution of a particular instruction, specified by one or both of the address of the instruction and the state of the processor when the instruction is executed.


Byte
An 8-bit data item.


Cache associativity
The number of locations in a cache set to which an address can be assigned. Each location is identified by its way value.


Cache hit
A memory access that can be processed at high speed because the data it addresses is already in the cache.


Cache level
The position of a cache in the cache hierarchy. In the ARM architecture, the lower numbered levels are those closest to the processor. For more information see Terms used in describing the maintenance operations on page B2-1274.

Cache line
The basic unit of storage in a cache. Its size in words is always a power of two, usually 4 or 8 words. A cache line must be aligned to a suitable memory boundary. A memory cache line is a block of memory locations with the same size and alignment as a cache line. Memory cache lines are sometimes loosely called cache lines.


Cache lockdown
Enables critical software and data to be loaded into the cache so that the cache lines containing them are not subsequently reallocated. It alleviates the delays caused by accessing a cache in a worst-case situation. This ensures that all subsequent accesses to the software and data concerned are cache hits and so complete quickly.


Cache miss
A memory access that cannot be processed at high speed because the data it addresses is not in the cache.


Cache sets
Areas of a cache, divided up to simplify and speed up the process of determining whether a cache hit occurs. The number of cache sets is always a power of two.


Cache way
A cache way consists of one cache line from each cache set. The cache ways are indexed from 0 to (Associativity-1).

Each cache line in a cache way is chosen to have the same index as the cache way. For example, cache way n consists of the cache line with index n from each cache set.


Coherence order
See Coherent.


Coherent
Data accesses from a set of observers to a byte in memory are coherent if accesses to that byte in memory by the members of that set of observers are consistent with there being a single total order of all writes to that byte in memory by all members of the set of observers. This single total order of all writes to that memory location is the coherence order for that byte in memory.


Condition code check
The process of determining whether a conditional instruction executes normally or is treated as a NOP. For an instruction that includes a condition code field, that field is compared with the condition flags to determine whether the instruction is executed normally. For a Thumb instruction in an IT block, the value of the ITSTATE register determines whether the instruction is executed normally.

See also Condition code field, Condition flags, Conditional execution.


Condition code field
A 4-bit field in an instruction that specifies the condition under which the instruction executes.

See also Condition code check.


Condition flags
The N, Z, C, and V bits of the APSR, CPSR, SPSR, or FPSCR. See the register descriptions for more information.


Conditional execution
When a conditional instruction starts executing, if the condition code check returns TRUE, the instruction executes normally. Otherwise, it is treated as a NOP.

See also Condition code check.


Context switch
The saving and restoring of computational state wh