转载 VHDL编程基础－ADC接口 ADC型号是ADS7842

最新推荐文章于 2019-03-15 09:34:43 发布

转载最新推荐文章于 2019-03-15 09:34:43 发布 · 265 阅读

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CC 4.0 BY-SA版权

原文链接：http://www.cnblogs.com/FPGA_DSP/archive/2010/01/31/1660394.html

本文详细介绍了使用状态机实现的FPGA控制ADS7842 ADC的VHDL程序，包括时钟管理、状态机设计、数据读取与锁存等关键环节。

VHDL编程基础－ADC接口

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刚刚写了一个FPGA控制ADC的程序，用状态机实现的。ADC型号是ADS7842。(仅供参考)

源程序如下：

LIBRARY ieee;
USE ieee.std_logic_1164.all;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
ENTITY ads7842 IS
PORT
(
  fclk : IN STD_LOGIC;       --?μí3ê±?ó
  din  : IN STD_LOGIC_VECTOR(11 DOWNTO 0); --à′×?ADS7842μ?êy?Y
  enable : IN STD_LOGIC;      --ADC?￡?éê1?üD?o? ??μ???óDD§
  rst  : IN STD_LOGIC;      --ADC?￡?é?′??D?o? ??μ???óDD§
  busy : IN STD_LOGIC;      --ADC×a???áê?D?o? é?éy??óDD§
  start : OUT STD_LOGIC;      --ADS7842 ×a???aê?D?o? ???μ??óDD§
  brd  : OUT STD_LOGIC;      --ADS7842 RDD?o? ???μ??óDD§
  bclk : OUT STD_LOGIC;      --ADS7842 1¤×÷ê±?ó
  dout : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); --?￡?éê?3?êy?Y
  adc_end : OUT STD_LOGIC       --×a???áê? êy?YóDD§D?o? ??μ???óDD§
);
END ENTITY;
------------------------------------------------------------------------------
------------------------------------------------------------------------------

ARCHITECTURE behav OF ads7842 IS
SIGNAL count: INTEGER range 0 to 19;
SIGNAL clk : STD_LOGIC;
TYPE ad_status IS(st0, st1, st2, st3, st4, st5 );
SIGNAL adc_current_state: ad_status;
SIGNAL adc_next_state: ad_status;
SIGNAL lock: STD_LOGIC;
SIGNAL adc_data:STD_LOGIC_VECTOR(11 DOWNTO 0);
BEGIN
------------------------------------------------------------------------------
------------ìá1?ADS78421¤×÷ê±?ó ???μí3ê±?ó20·??μ μ?μ?2.5MHZ-------------------
------------------------------------------------------------------------------
DCLK:PROCESS( fclk )
BEGIN
  IF ( fclk 'EVENT AND fclk = '1') THEN
   IF count = 19 THEN
    count <= 0;
    clk <= NOT clk;
   ELSE
    count <= count + 1;
          END IF;
        ELSE
   NULL;
        END IF;
END PROCESS DCLK;
bclk <= clk;
------------------------------------------------------------------------------
-------------------------ADS78422é?ù????×′ì??ú--------------------------------
------------------------------------------------------------------------------

ADC:PROCESS( adc_current_state, busy, enable )
BEGIN
          --×′ì??ú?′??
  IF(rst = '1' ) THEN
   adc_next_state <= st0;
  ELSE
   CASE adc_current_state IS
          --A/D×a??3?ê??ˉ
   WHEN st0 =>
    start <= '1';
    brd <= '1';
    lock <= '0';
    adc_end <= '0';
    IF(enable = '1') THEN
     adc_next_state <= st1;
    ELSE
     adc_next_state <= st0;
    END IF;

   WHEN st1 =>     --?aê?×a??
    start <= '0';
    brd <= '1';
    lock <= '0';
    adc_end <= '0';
    adc_next_state <= st2;

   WHEN st2 =>     --?astartD?o??ó3ùò???ê±?ó?ü?ú
    start <= '0';
    brd <= '1';
    lock <= '0';
    adc_end <= '0';
    IF(busy = '0') THEN
     adc_next_state <= st3;
    ELSE
     adc_next_state <= st2;
    END IF;

   WHEN st3 =>
    start <= '1';
    brd <= '1';
    lock <= '0';
    adc_end <= '0';
    IF(busy = '1') THEN --×a???áê?￡?×a??ò???×′ì?
     adc_next_state <= st4;
    ELSE      --?′?áê?￡??ò?ìD?μè′y
     adc_next_state <= st3;
    END IF;

   WHEN st4 =>     --?a??ê?3?êy?Yê1?üD?o?
    start <= '1';
    brd <= '0';
    lock <= '0';
    adc_end <= '0';
    adc_next_state <= st5;

   WHEN st5 =>     --?a??êy?Y??′?D?o?￡??a??×a???áê?D?o?
    start <= '1';
    brd <= '0';
    lock <= '1';
    adc_end <= '1';
    adc_next_state <= st0;

     WHEN OTHERS => adc_next_state <= st0;

   END CASE;
  END IF;
END PROCESS ADC;
------------------------------------------------------------------------------
------------------------ADS78422é?ù????×′ì??úê±Dòμ??·-------------------------
------------------------------------------------------------------------------
AD_STATE:PROCESS( fclk )
BEGIN

  IF( fclk'event AND fclk = '1') THEN
   adc_current_state <= adc_next_state;
  END IF;
END PROCESS AD_STATE;
------------------------------------------------------------------------------
---------------------------ADS78422é?ùêy?Y??′?--------------------------------
------------------------------------------------------------------------------
DATA_LOCK:PROCESS( lock )
BEGIN
  IF lock'event AND lock = '1' THEN
   adc_data <= din;
   --lock <= '0';
   --adc_end <= '1';
  --ELSE
   --adc_end <= '0';
  END IF;
END PROCESS DATA_LOCK;

dout <= adc_data;

END behav;

功能仿真图：

主要信号：

adc_end：转换结束，数据有效信号，高电平有效

bclk：ADC转换时钟(2.5MHZ)

brd：ADC /RD信号，读数据使能，下降沿有效

busy：ADC转换信号，可用busy上升沿锁存数据

din：接ADC数据端口

dout：用于数据输出

enable：模块使能，高电平有效

fclk：系统时钟 50MHZ

rst：模块复位信号，高电平复位

start：ADC转换开始信号，下降沿开始，接ADC的/WR脚。

转载于:https://www.cnblogs.com/FPGA_DSP/archive/2010/01/31/1660394.html