敏感信号与判断条件冲突引起的错误

 

Error (10200): Verilog HDL Conditional Statement error at Clk_pwm_div.v(14): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct

always@(posedge clk or posedge rst )
if( rst==0 )temp <= 8'd0;

敏感信号posedge rst 与判断条件rst==0 有冲突

转载于:https://www.cnblogs.com/agllero/p/4448511.html