该文描述了一种容错计算机架构，通过主数据总线连接多个传统计算机子系统，减少硬件故障的影响。架构中包含一个中央处理器子系统，由多个并行且同步运行的中央处理模块组成。其中一个模块作为主中央处理模块，负责读取和写入主数据总线。每个模块内部有机制比较主数据总线和模块内的次要总线数据，以检测不一致，即硬件故障。检测到不一致时，各模块会生成状态输出，反映模块故障的概率。所有模块通过同步总线相互连接，传递状态输出，以实现故障定位。
摘要：
A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules. Each central processing module contains a means by which the module can compare data on the main data bus with data on a secondary bus within each module in order to determine if there is an inconsistency indicating a hardware fault. If such an inconsistency is detected, each module generates state outputs which reflect the probability that a particular module is the source of the fault. A synchronization bus which is separate from the main data bus interconnects the central processing modules and transmits the state outputs from each module to every other central processing module.
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