432偏计算机编程,谈谈MSP432的编程方法

此博客介绍了如何使用MSP432P401通过I2C总线连接两个微控制器,主设备向四个不同地址的从设备发送定制数据。展示了中断处理、配置步骤和代码实现。

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本帖最后由 平湖秋月 于 2015-5-18 21:16 编辑

基于寄存器的编程示例

//******************************************************************************

//  MSP432P401 Demo - eUSCI_B0 I2C Master TX bytes to Multiple Slaves

//

//  Description: This demo connects two MSP432's via the I2C bus.

//  The master transmits to 4 different I2C slave addresses 0x0A,0x0B,0x0C&0x0D.

//  Each slave address has a specific related data in the array TXData[].

//  At the end of four I2C transactions the slave address rolls over and begins

//  again at 0x0A.

//

//  Use with msp432p401_euscia0_i2c_multislave.c

//

//                                /|\  /|\

//               MSP432P401      10k  10k     MSP432P401

//                   slave         |    |        master

//             -----------------   |    |   -----------------

//            |     P1.6/UCB0SDA||P1.6/UCB0SDA     |

//            |                 |  |       |                 |

//            |                 |  |       |                 |

//            |     P1.7/UCB0SCL||P1.7/UCB0SCL     |

//            |                 |          |                 |

//

//   Wei Zhao

//   Texas Instruments Inc.

//   June 2014

//   Built with Code Composer Studio V6.0

//******************************************************************************

#include "msp.h"

#include uint8_t TXData[]= {0xA1,0xB1,0xC1,0xD1};        // Pointer to TX data

uint8_t SlaveAddress[]= {0x0A,0x0B,0x0C,0x0D};

uint8_t TXByteCtr;

uint8_t SlaveFlag = 0;

int main(void)

{

volatile uint32_t i;

WDTCTL = WDTPW | WDTHOLD;                         // Stop watchdog timer

// Configure Pins for I2C

P1SEL0 |= BIT6 | BIT7;                            // I2C pins

__enable_interrupt();

NVIC_ISER0 = 1 << ((INT_EUSCIB0 - 16) & 31); // Enable eUSCIB0 interrupt in NVIC module

// Configure USCI_B0 for I2C mode

UCB0CTLW0 |= UCSWRST;                             // put eUSCI_B in reset state

UCB0CTLW0 |= UCMODE_3 | UCMST;                    // I2C master mode, SMCLK

UCB0BRW = 0x0018;                                 // baudrate = SMCLK /24

UCB0CTLW0 &=~ UCSWRST;                            // clear reset register

UCB0IE |= UCTXIE0 | UCNACKIE;                     // transmit and NACK interrupt enable

SlaveFlag =0;

while(1)

{

SCB_SCR |= SCB_SCR_SLEEPONEXIT;                   // Don't wake up on exit from ISR

for (i = 1000; i > 0; i--);                       // Delay between transmissions

UCB0I2CSA = SlaveAddress[SlaveFlag];              // configure slave address

TXByteCtr = 1;                                    // Load TX byte counter

while (UCB0CTLW0 & UCTXSTP);                      // Ensure stop condition got sent

UCB0CTLW0 |= UCTR | UCTXSTT;                      // I2C TX, start condition

__sleep();

__no_operation();

// Change Slave address

SlaveFlag++;

if (SlaveFlag>3)                                  // Roll over slave address

{

SlaveFlag =0;

}

}

}

// I2C interrupt service routine

void eUSCIB0IsrHandler(void)

{

if (UCB0IFG & UCNACKIFG)

{

UCB0IFG &= ~ UCNACKIFG;

UCB0CTL1 |= UCTXSTT;                  // I2C start condition

}

if (UCB0IFG & UCTXIFG0)

{

UCB0IFG &= ~ UCTXIFG0;

if (TXByteCtr)                                // Check TX byte counter

{

UCB0TXBUF = TXData[SlaveFlag];            // Load TX buffer

TXByteCtr--;                              // Decrement TX byte counter

}

else

{

UCB0CTLW0 |= UCTXSTP;                     // I2C stop condition

UCB0IFG &= ~UCTXIFG;                      // Clear USCI_B0 TX int flag

SCB_SCR &= ~SCB_SCR_SLEEPONEXIT;          // Wake up on exit from ISR

}

}

}

MSP432 低功耗高性能并存10.1 Digital I/O Introduction The digital I/O features include: • Independently programmable individual I/Os • Any combination of input or output • Individually configurable interrupts for ports (available for certain ports only) • Independent input and output data registers • Individually configurable pullup or pulldown resistors • Wake-up capability from ultra-low power modes (available for certain ports only) • Individually configurable high drive I/Os (available for certain I/Os only) Devices within the family may have up to eleven digital I/O ports implemented (P1 to P10 and PJ). Most ports contain eight I/O lines; however, some ports may contain less (see the device-specific data sheet for ports available). Each I/O line is individually configurable for input or output direction, and each can be individually read or written. Each I/O line is individually configurable for pullup or pulldown resistors. Certain ports have interrupt and wake-up capability from ultra-low power modes (see device specific data sheet for ports with interrupt and wake-up capability). Each interrupt can be individually enabled and configured to provide an interrupt on a rising or falling edge of an input signal. All interrupts are fed into an encoded Interrupt Vector register, allowing the application to determine which sub-pin of a port has generated the event. Individual ports can be accessed as byte-wide ports or can be combined into half-word-wide ports. Port pairs P1 and P2, P3 and P4, P5 and P6, P7 and P8, and so on, are associated with the names PA, PB, PC, PD, and so on, respectively. All port registers are handled in this manner with this naming convention. The main exception are the interrupt vector registers, for example, interrupts for ports P1 and P2 must be handled through P1IV and P2IV, PAIV does not exist. When writing to port PA with half-word operations, all 16 bits are written to the port. When writing to the lower byte of port PA using byte operations, the upper byte remains unchanged. Similarly, writing to the upper byte of port PA using byte instructions leaves the lower byte unchanged. When writing to a port that contains less than the maximum number of bits possible, the unused bits are don't care. Ports PB, PC, PD, PE, and PF behave similarly.
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