IAR+ARM出现synchronous external abort错误原因分析(2)

问题描述:当程序某个高优先级的中断触发后(如pcie中断),或者底层接口物理链路初始化的一瞬间,原本正常运行的程序突然进入异常中断程序,并报出“synchronous external abort”错误。

问题原因分析:通过排查代码,发现是由于串口接收中断服务函数中将接收缓冲区指定为一个固定长度的结构体(例如:仅容纳一帧串口数据的13个字节)。结果发现在高优先级中断触发或底层接口物理链路初始化时,cpu被占用,未能够及时响应串口接收中断,导致下次正常进入串口接收中断函数后,一次读取出两帧数据(26个字节)。这两帧数据直接导致缓冲区结构体的内存空间溢出,所以才会报出“synchronous external abort”错误。

解决办法:不再使用固定长度的结构体作为接收缓冲区,而是使用一个较长的数组作为缓冲区(确保长度大于理论最大接收长度),这样就算有一次串口接收中断未响应,也不会出现上述错误。

This manual describes the ARM® architecture v8, ARMv8. The architecture describes the operation of an ARMv8-A Processing element (PE), and this manual includes descriptions of: • The two Execution states, AArch64 and AArch32. • The instruction sets: — In AArch32 state, the A32 and T32 instruction sets, that are compatible with earlier versions of the ARM architecture. — In AArch64 state, the A64 instruction set. • The states that determine how a PE operates, including the current Exception level and Security state, and in AArch32 state the PE mode. • The Exception model. • The interprocessing model, that supports transitioning between AArch64 state and AArch32 state. • The memory model, that defines memory ordering and memory management. This manual covers a single architecture profile, ARMv8-A, that defines a Virtual Memory System Architecture (VMSA). • The programmers’ model, and its interfaces to System registers that control most PE and memory system features, and provide status information. • The Advanced SIMD and floating-point instructions, that provide high-performance: — Single-precision and double-precision floating-point operations. — Conversions between double-precision, single-precision, and half-precision floating-point values. — Integer, single-precision floating-point, and in A64, double-precision vector operations in all instruction sets. — Double-precision floating-point vector operations in the A64 instruction set. • The security model, that provides two security states to support secure applications. • The virtualization model, that support the virtualization of Non-secure operation. • The Debug architecture, that provides software access to debug features.
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