[RISC-V]Standard Extensions

RISC-V架构提供了一系列标准扩展,以满足不同设计目标,如能量、面积、性能和存储需求。核心ISA默认必须实现,提供优化机会。此外,还有如乘法/除法(M)、原子操作(A)、浮点运算(F/D/G/Q)、压缩指令(C)、位操作(B)等扩展,各具特色并可根据需求选择实现。这些扩展丰富了RISC-V的功能,使其能应用于各种场景。

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RISC-V has standardized a series of standard extensions beyond the integer base instructions which can be implemented or omitted as desired depending on the design goals (e.g. energy/area/performance/storage goals).

Overview

By default, only the core ISA must be implemented presenting great opportunity for area and energy optimization. However, additional functionality is sometimes desired. RISC-V comes with a series of standard extensions that enable additional functionality beyond the core ISA such as floating point and operations and bit manipulation. Extensions can be implemented and omitted as desired. Those extensions are:

NameDescriptionVersionStatusInstruction Count
RV32IBase Integer Instruction Set - 32-bit2.1Frozen49
RV32EBase Integer Instruction Set (embedded) - 32-bit, 16 registers1.9OpenSame as RV32I
RV64IBase Integer Instruction Set - 64-bit2.0Frozen14
RV128IBase Integer Instruction Set - 128-bit1.7Open14
Extension
MStandard Extension for Integer Multiplication and Division2.0Frozen8
AStandard Extension for Atomic Instructions2.0Frozen11
FStandard Extension for Single-Precision Floating-Point2.0Frozen25
DStandard Extension for Double-Precision Floating-Point2.0Frozen25
GShorthand for the base and above extensionsn/an/an/a
QStandard Extension for Quad-Precision Floating-Point2.0Frozen27
LStandard Extension for Decimal Floating-Point0.0OpenUndefined Yet
CStandard Extension for Compressed Instructions2.0Frozen36
BStandard Extension for Bit Manipulation0.90Open42
JStandard Extension for Dynamically Translated Languages0.0OpenUndefined Yet
TStandard Extension for Transactional Memory0.0OpenUndefined Yet
PStandard Extension for Packed-SIMD Instructions0.1OpenUndefined Yet
VStandard Extension for Vector Operations0.7Open186
NStandard Extension for User-Level Interrupts1.1Open3
HStandard Extension for Hypervisor0.0Open2
SStandard Extension for Supervisor-level Instructions1.12Open7

Naming Convention

RISC-V defines an exact order that must be used to define the RISC-V ISA subset:
RV [32, 64, 128] I, M, A, F, D, G, Q, L, C, B, J, T, P, V, N

For example, RV32IMAFDQC is legal, whereas RV32IMAFDCQ is not.

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