VHDL——数字秒表，定时器

最新推荐文章于 2025-06-09 16:02:02 发布

原创最新推荐文章于 2025-06-09 16:02:02 发布 · 4.7k 阅读

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#signal #library #integer

本文介绍了一个数字秒表的设计实现，采用Verilog HDL语言完成毫秒及秒的计时功能。通过两个模块分别实现了毫秒级和秒级的计时，并在顶层文件中进行了实例化。未来计划增加分钟和小时的计时功能。

数字秒表，因为仿真的问题，现在只有毫秒和秒。如果分和小时都弄上，仿真要出效果得走半天，所以就删掉了

现在只能按下复位键后计时，以后慢慢添加更多功能，包括保存，多次计时等

--毫秒功能 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity time_ms is port( clk ,reset :in std_logic; ms_out :out std_logic ); end entity; architecture rtl_ms of time_ms is signal count_ms :integer :=0; begin process(clk) begin if reset='0' then ms_out<='0'; count_ms<=0; elsif clk'event and clk='1' then if count_ms=10 then --设成1000仿真受不了了 ms_out<='1'; count_ms<=0; else count_ms<=count_ms+1; ms_out<='0'; end if; end if; end process; end rtl_ms;

--秒功能 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity time_sec is port( clk ,reset :in std_logic; ms_in :in std_logic; sec_out :out std_logic ); end entity; architecture rtl_sec of time_sec is signal count_sec :integer :=0; signal tmp :std_logic; begin -- count_ms <=ms_in; tmp<=ms_in; process(clk) begin if reset='0' then -- tmp <='0'; sec_out <='0'; count_sec<=0; elsif clk'event and clk='1' then if tmp='1' then count_sec<=count_sec+1; sec_out<='0'; if count_sec=20 then --和上面同样的道理 sec_out<='1'; count_sec<=0; end if; end if; end if; end process; end rtl_sec;

--顶层例化 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity clock is port( clk,reset :in std_logic; time_out :out std_logic ); end entity; architecture rtl of clock is signal tmp1 :std_logic; component time_ms is port( clk ,reset :in std_logic; ms_out :out std_logic ); end component; component time_sec is port( clk ,reset :in std_logic; ms_in :in std_logic; sec_out :out std_logic ); end component; begin --例化这里我花了好久时间才弄好 u1:time_ms port map(clk=>clk,reset=>reset,ms_out=>tmp1); u2:time_sec port map(clk=>clk,reset=>reset,ms_in=>tmp1,sec_out=>time_out); end architecture;

仿真结果如下图