VHDL——简单同步FIFO

功能：存入数据按顺序排放，存储器全满时给出信号并拒绝继续存入，全空时也给出信号并拒绝读出；读出时按先进先出原则；存储数据一旦读出就从存储器中消失

 

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; entity fifo is port( datain :in std_logic_vector(7 downto 0); push,pop :in std_logic; reset,clk :in std_logic; full :out std_logic; dataout :out std_logic_vector(7 downto 0) ); end entity; architecture rtl of fifo is type arraylogic is array(15 downto 0) of std_logic_vector(7 downto 0); signal data :arraylogic; signal fi :std_logic; signal wp,rp :natural range 0 to 15; signal selfunction :std_logic_vector(1 downto 0); begin main:process(clk,reset,pop,push) begin full<=fi; -- empty<=ei; selfunction <=push&pop; --?? if reset='1' then wp <=0; --???? rp <=0; fi <='0'; --?????0?????? dataout <=(others=>'0'); --???FIFO?? for i in 0 to 15 loop data(i)<="00000000"; end loop; elsif clk'event and clk='1' then if (fi='0' and selfunction="10" and wp<15) then --FIFO??????????? data(wp) <=datain; wp <=wp+1; end if; if (fi='0' and selfunction="10" and wp=15) then data(wp) <=datain; wp <=0; fi <='1'; end if; if (fi='1' and selfunction="01" and rp<15) then dataout<=data(rp); rp<=rp+1; end if; if (fi='1' and selfunction="01" and rp=15) then dataout<=data(rp); rp<=0; fi<='0'; end if; end if; end process; end rtl;

只能实现最基本的功能，还有很多不完善的地方，以后慢慢改进了