CEG2136: Computer Architecture I

CEG2136: Computer Architecture I

LAB 4                      BASIC COMPUTER ORGANIZATION

1. Objectives

In this laboratory, students will analyse the structure of a basic computer, will devise, design, implement, simulate in Quartus and, if will be physically present in the lab, will test experimentally its control unit on Altera platform; furthermore, students will use opcodes to write simple programs in machine  code.  The  design  must  function  in  simulation,  and  also  on  the  DE2-115  Altera development board, if physically present in the lab.

2. Equipment and Supplies:

* Quartus II (student edition or web edition)

* Altera DE2-115 board with

- USB-blaster cable

- Power supply 12 VDC, 2A

3. References

.    You are provided with all the .bdf files, except one that describes the combinational circuits which generates the output and transition functions of the Control Unit and which you are expected to conceive and develop. Their logic diagrams are annexed to this document.

.     Chapters 5 and 6 of the textbook: Computer Systems Structures, Morris Mano, 3rd edition, 1993, ISBN 0-13-175563-3.

.    The course notes

.    The user guide of the Altera DE2-115 development kit is provided in the Laboratories > Documentation section of your CEG2136 Virtual Campus.

4. The Structure of the Basic Computer

4.1 General View

This laboratory implements a computer having a structure that is very close to the one presented in figure 5.4 on page 130 of your textbook. However, there are two major differences:

1.   The designed computer’s memory (storing both programs and data) has a capacity of 256 words of

8 bits (256 x 8). In the textbook, the BASIC computer has a memory with words of 16 bits, each word being capable of storing one memory-reference instruction (which consists there of a 4-bit opcode and a 12-bit memory address). In this lab, a memory-reference instruction is 2 byte long as well, but the msb byte carries the opcode, while the lsb byte contains the operand address (8 bits are enough to address a memory space of 28 = 256 memory locations); as such, a 2-byte memory- reference instruction is stored in 2 consecutive memory locations (two 1-byte words).

Consequently, two successive READ cycles are needed to fetch a memory-reference instruction: first to get the opcode, and the second to get the address of the data that the opcode will use.

2.   The second major difference consists in the additional circuits which will allow a user to visualize the contents of the memory independently of having a program running or not on the DE2-115 board.

User can preset the DIP switches on the board with the memory address to be visualized. Before the fetch phase of each instruction, the BASIC computer reads the contents of the memory location pointed at by the DIP switches on the board and shows it in hexadecimal format on the 7 segment display of the board.

The block diagram of your computer is presented in Figure 1. The .bdf files of all the component blocks, except the Instruction Decoder (lab_controller of CU), will be provided. The Control Unit functions in accord with a time sequence which is generated by the sequence counter (SC) that plays the role of FSM state register. The SC initial state is 0; it restarts counting from 0 at the beginning of each instruction of a program and it is reset to 0 once that instruction is finished. A decoder converts the 4- bit output of the SC into time-signals, distinct for each possible output (for example, when the SC output is 0010, then the T2  output of the decoder will go high, if not, it will remain low for any other combination); this combination of the SC and its decoder implement a One-hot encoded state register. The control commands for the Datapath are synthesized by the Instruction Decoder as (FSM output) functions in terms of the contents of the IR, DR and other signals from the Datapath; a set of gates (AND, OR, and NOT) forms the Instruction Decoder. As some CU outputs are of Mealy type, a bank of buffer registers (Control Register) is used to insure a duration of one clock period for the control commands that are generated by the CU, and to synchronize them with the system clock.

Figure 1:  Computer block diagram

The following sequence of steps (grouped in 3 sets –&n