Plx使用手册学习----11 PlxPci_DmaTransferUserBuffer

Syntax:
 

PLX_STATUS
PlxPci_DmaTransferUserBuffer(
PLX_DEVICE_OBJECT *pDevice,
U8 channel,
PLX_DMA_PARAMS *pDmaParams,
U64 Timeout_ms
);

PLX Chip Support:
9054, 9056, 9080, 9656, 8311, & 8000 DMA
* On some versions of Windows (e.g. 2003 Server) or system with more than 4GB of RAM, the physical address
of some user mode buffer pages may require 64-bit addressing. If this is detected, the PLX driver will
automatically use features in the PLX chip to access these pages. For legacy PCI DMA chips, PCI dualaddressing is enabled. For newer PCI Express switch DMA, extended descriptors are used as needed. Dualaddressing is not supported on the PLX 9080 device; therefore, the API will return an error if 64-bit is required
with this device.
Description:

使用DMA通道传输用户提供的缓冲区。使用DMA信道的SGL模式，

但这对应用程序是透明的。

功能工作如下：

−PLX驱动程序获取所提供的用户模式缓冲区并将其页面锁定到内存中。

—缓冲区通常分散在非连续页中的整个内存中。因此，驾驶员

然后确定缓冲区内存每页的物理地址，并创建一个SGL

每个页面的描述符。描述符被放置到内部驱动程序分配的缓冲区中。

−DMA信道被编程为从第一个描述符开始。

−DMA传输完成后，将发生中断，然后驱动程序将执行所有清理任务。

Transfers a user-supplied buffer using the DMA channel. SGL mode of the DMA channel is used, but this is
transparent to the application. The function works as follows:
- The PLX driver takes the provided user-mode buffer and page-locks it into memory.
- The buffer is typically scattered throughout memory in non-contiguous pages. As a result, the driver
then determines the physical address of each page of memory of the buffer and creates an SGL
descriptor for each page. The descriptors are placed into an internal driver allocated buffer.
- The DMA channel is programmed to start at the first descriptor.
- After DMA transfer completion, an interrupt will occur and the driver will then perform all cleanup tasks.
Parameters:
pDevice
Pointer to an open device
channel
The open DMA channel number to use for the transfer
pDmaParams
A pointer to a structure containing the DMA transfer parameters
Timeout_ms
Specifies the timeout, in milliseconds, for the function to wait for DMA completion.
If 0, the API returns immediately after starting the DMA transfer and does not wait for its completion.
To have the function wait indefinitely for DMA completion, use the value PLX_TIMEOUT_INFINITE.
5-39
Return Codes:

Code	Description
ApiSuccess	The function returned successfully
ApiNullParam	One or more parameters is NULL
ApiInvalidDeviceInfo	The device object is not valid
ApiPowerDown	The PLX device is in a power state that is lower than required for this function
ApiDmaChannelInvalid	The DMA channel is not supported by the PLX chip
ApiDmaChannelUnavailable	The DMA channel was not previously opened by the caller
ApiDmaInProgress	The DMA transfer is currently in-progress
ApiWaitTimeout	No interrupt was received to signal DMA completion
ApiDmaSglPagesGetError	The driver was unable to obtain the page list for the user- mode buffer
ApiDmaSglPagesLockError	The driver was unable to page lock the user-mode buffer
ApiInsufficientResources	The driver was unable to allocate an internal buffer to store SGL descriptors
ApiDeviceInUse	The DMA channel is open but owned by another calling thread or process

Notes:
The driver will always enable the DMA channel interrupt when this function is used. This is required so the
driver can perform cleanup routines, such as unlock the buffer and release descriptors, after the transfer has
completed.
The PLX_DMA_PARAMS structure contains members whose meanings may differ or even be ignored
depending on the DMA transfer type selected by the calling function.
PLX_DMA_PARAMS:

Structure Element	Description
UserVa	Virtual address of the user-mode buffer to transfer
AddrSource	Ignored
AddrDest	Ignored
PciAddr	(9000 DMA) Ignored (8000 DMA) Specifies the PCI address to transfer to/from, depending upon Direction
LocalAddr	(9000 DMA) The Local address for the transfer
ByteCount	The number of bytes to transfer
Direction	Direction of the transfer. Refer to PLX_DMA_DIR
bConstAddrSrc	(8000 DMA) Keeps the source address constant
bConstAddrDest	(8000 DMA) Keeps the destination address constant
bForceFlush	(8000 DMA) DMA engine will issue a Zero-length TLP to flush final writes.
bIgnoreBlockInt	Ignored. PLX driver always enables DMA done interrupt to cleanup SGL

Usage:

U8 *pBuffer;
PLX_DMA_PARAMS DmaParams;
// Allocate a 500k buffer
pBuffer = malloc(500 * 1024);
// Clear DMA parameters
memset( DmaParams, 0, sizeof(PLX_DMA_PARAMS) );
// Setup DMA parameters (9000 DMA)
DmaParams.UserVa = (PLX_UINT_PTR)pBuffer;
DmaParams.ByteCount = (500 * 1024);
if (pDevObj->Key.PlxChipFamily == PLX_FAMILY_BRIDGE_P2L)
{
// 9000/8311 DMA
DmaParams.LocalAddr = 0x0;
DmaParams.Direction = PLX_DMA_LOC_TO_PCI;
}
else
{
// 8000 DMA
DmaParams.PciAddr = 0x1F000000;
DmaParams.Direction = PLX_DMA_PCI_TO_USER;
}
rc =
PlxPci_DmaTransferUserBuffer(
pDevice,
0, // Channel 0
&DmaParams, // DMA transfer parameters
(3 * 1000) // Specify time to wait for DMA completion
);
if (rc != ApiSuccess)
{
if (rc == ApiWaitTimeout)
// Timed out waiting for DMA completion
else
// ERROR - Unable to perform DMA transfer
}