Device Registration and Initialization

本文探讨了网络接口控制器(NIC)的设备驱动程序如何在启动时初始化,并在模块加载时进行动态注册。同时,文章还讨论了热插拔网络设备的注册与卸载过程,以及设备名称的分配原则。

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When a Device Is Registered

Loading an NIC’s device driver
An NIC’s device driver is initialized at boot time if it is built into the kernel, and at runtime if it is loaded as a module. Whenever initialization occurs, all the NICs controlled by that driver are registered.
Inserting a hot-pluggable network device
When a user inserts a hot-pluggable NIC, the kernel notifies its driver, which then registers the device. (For the sake of simplicity, we’ll assume the device driver is already loaded.)

When a Device Is Unregistered

Unloading an NIC device driver
This can be done only for drivers loaded as modules, of course, not for those built into the kernel. When the administrator unloads an NIC’s device driver, all the associated NICs must be unregistered.

Removing a hot-pluggable network device
When a user removes a hot-pluggable NIC from a system whose running kernel has support for hot-pluggable devices, the network device is unregistered

Allocating net_device Structures

Network devices are defined with net_device structures.These data structures are allocated with alloc_netdev, defined in net/core/dev.c, which requires three input parameters:

Size of private data structure
the net_device data structure can be extended by device drivers with a private data block to store the driver’s parameters. This parameter specifies the size of the block.
Device name
This may be a partial name that the kernel will complete through some scheme that ensures unique device names.
Setup routine
This routine is used to initialize a portion of the net_device’s fields.
The return value is a pointer to the net_device structure allocated, or NULL in case of errors.

Every device is assigned a name that depends on the device type and that, to be unique, contains a number that is assigned sequentially as devices of the same type are registered. Ethernet devices, for instance, are called eth0, eth1, and so on. A single device may be called with different names depending on the order with which the www.it-devices are registered. For instance, if you had two cards handled by two different modules, the names of the devices would depend on the order in which the two modules were loaded. Hot-pluggable devices lend themselves particularly to unanticipated name changes.

Skeleton of NIC Registration and Unregistration

Device Initialization


翻译 The DDR5 SDRAM is a high-speed dynamic random-access memory. To ease transition from DDR4 to DDR5, the introductory density (8Gb) shall be internally configured as 16-bank, 8 bank group with 2 banks for each bank group for x4/x8 and 8-bank, 4 bank group with 2 banks for each bankgroup for x16 DRAM. When the industry transitions to higher densities (=>16Gb), it doubles the bank resources and internally be configured as 32-bank, 8 bank group with 4 banks for each bank group for x4/x8 and 16-bank, 4 bank group with 4 banks for each bankgroup for x16 DRAM. The DDR5 SDRAM uses a 16n prefetch architecture to achieve high-speed operation. The 16n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR5 SDRAM consists of a single 16n-bit wide, eight clock data transfer at the internal DRAM core and sixteen corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write operation to the DDR5 SDRAM are burst oriented, start at a selected location, and continue for a burst length of sixteen or a ‘chopped’ burst of eight in a programmed sequence. Operation begins with the registration of an ACTIVATE Command, which is then followed by a Read or Write command. The address bits registered with the ACTIVATE Command are used to select the bank and row to be activated (i.e., in a 16Gb part, BG0-BG2 in a x4/8 and BG0-BG1 in x16 select the bankgroup; BA0-BA1 select the bank; R0-R17 select the row; refer to Section 2.7 for specific requirements). The address bits registered with the Read or Write command are used to select the starting column location for the burst operation, determine if the auto precharge command is to be issued (CA10=L), and select BC8 on-the-fly (OTF), fixed BL16, fixed BL32 (optional), or BL32 OTF (optional) mode if enabled in the mode register. Prior to normal operation, the DDR5 SDRAM must be powered up and initialized in a predefined manner. The following sections provide detailed information covering device reset and initialization, register definition, command descriptions, and device operation.
最新发布
03-08
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