ATPG
-Automatic Test Pattern Generation
CDC
-Clock-Domain Crossing
CMSIS
-Cortex Microcontroller Software Interface Standard
CPF
-Common Power Format
CSSoC
-CoreSight SoC
CTI
-Cross Trigger Interface
CTM
-Cross Trigger Matrix
DAP
-Debug Access Port
DCS
-Debug Component Slave
DFT
-Design for Test
dni
-data not instruction
DP
-Debug Port
DRC
-Design Rule Check
DSM
-Design Simulation Model
ECO
-Engineering Change Order
EDS
-External Debug Slave
GPIO
-General Purpose Input/Output
HWF
-Half Word Fetching
IIM
-Integration and Implementation Manual
IK
-Integration Kit
ISR
-Interrupt Service Routine
LVS
-Layout Versus Schematic
MCU
-Microcontroller Unit
MPU
-Memory Protection Unit
MTB
-Micro Trace Buffer
NIC
-Network InterConnect
OVL
-Open Verification Library
PIL
-Processor Integration Layer
PPB
-Private Peripheral Bus
RTL
-Register Transfer Level
SDA
-Standard Delay Format
SI
-Scan-In
SO
-Scan-Out
SoC
-System-on-Chip
SRPG
-State Retention and Power Gating
STA
-Static Timing Analysis
UPF
-Unified Power Format
WIC
-Wakeup Interrupt Controller
IC
-Integrated Cirucit
PPS
-Packet Per Second
HDL
-Hardware Description Languae
HDVL
-Hardware Description and Verification Language
WDT
-Watch Dog Timer
TAP
-Test Access Port
SPI
-Serial Peripheral Interface
UART
-Universal Asynchronous Receiver/Transmitter
TCL
-Tool Command Language
PLL
-Phase Lock Loop
CORDIC
-Coordinate Rotation Digital Computer
NCO
-Numerical Controlled Oscillator
DDS
-Direct Digital Synthesizer
FM
-Frequency Modulation
AWGN
-Additive White Gaussian Noise
BICM
-Bit-Interleaved Coded Modulation
CRC
-Cyclic Redundancy Check
FCS
-Frame Check Sequence
RCPC
-Rate-compatible Punctured Convolutional Codes
ZTCC
-Zero-Tail terminated Convolutional Codes
TBCC
-Tail Biting Convolutional Coding
BMU
-Branch Metric Unit
ACSU
-Add-Compare-Select Unit
SMU
-Survivor Management Unit
TBU
-Trace Back Unit
CU
-Control Unit
ACG
-Architectural Clock Gating