ADALM-PlutoSDR 上手（五）u-boot devices tree分析

最新推荐文章于 2024-05-16 15:47:42 发布

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最新推荐文章于 2024-05-16 15:47:42 发布 · 2k 阅读

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本文详细分析了ADALM-PlutoSDR在u-boot阶段的设备树配置，重点探讨了zynq-pluto-sdr.dts及其包含的zynq-7000.dtsi和skeleton.dtsi文件，揭示了Zynq-7000 SoC在PlutoSDR模块中的设备树组织结构。

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在PlutoSDR模块的zynq u-boot阶段的 devices tree

zynq-pluto-sdr.dts
–>zynq-7000.dtsi
–>skeleton.dtsi

zynq-7000.dtsi

/*
 * Xilinx Zynq 7000 DTSI
 * Describes the hardware common to all Zynq 7000-based boards.
 *
 *  Copyright (C) 2011 - 2015 Xilinx
 *
 * SPDX-License-Identifier: GPL-2.0+
 */
/include/ "skeleton.dtsi"

/ {
    compatible = "xlnx,zynq-7000";

    cpus {
        #address-cells = <1>;
        #size-cells = <0>;

        cpu0: cpu@0 {
            compatible = "arm,cortex-a9";
            device_type = "cpu";
            reg = <0>;
            clocks = <&clkc 3>;
            clock-latency = <1000>;
            cpu0-supply = <&regulator_vccpint>;
            operating-points = <
                /* kHz    uV */
                666667  1000000
                333334  1000000
            >;
        };

        cpu1: cpu@1 {
            compatible = "arm,cortex-a9";
            device_type = "cpu";
            reg = <1>;
            clocks = <&clkc 3>;
        };
    };

    pmu {
        compatible = "arm,cortex-a9-pmu";
        interrupts = <0 5 4>, <0 6 4>;
        interrupt-parent = <&intc>;
        reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
    };

    regulator_vccpint: fixedregulator@0 {
        compatible = "regulator-fixed";
        regulator-name = "VCCPINT";
        regulator-min-microvolt = <1000000>;
        regulator-max-microvolt = <1000000>;
        regulator-boot-on;
        regulator-always-on;
    };

    amba: amba {
        u-boot,dm-pre-reloc;
        compatible = "simple-bus";
        #address-cells = <1>;
        #size-cells = <1>;
        interrupt-parent = <&intc>;
        ranges;

        adc: adc@f8007100 {
            compatible = "xlnx,zynq-xadc-1.00.a";
            reg = <0xf8007100 0x20>;
            interrupts = <0 7 4>;
            interrupt-parent = <&intc>;
            clocks = <&clkc 12>;
        };

        can0: can@e0008000 {
            compatible = "xlnx,zynq-can-1.0";
            status = "disabled";
            clocks = <&clkc 19>, <&clkc 36>;
            clock-names = "can_clk", "pclk";
            reg = <0xe0008000 0x1000>;
            interrupts = <0 28 4>;
            interrupt-parent = <&intc>;
            tx-fifo-depth = <0x40>;
            rx-fifo-depth = <0x40>;
        };

        can1: can@e0009000 {
            compatible = "xlnx,zynq-can-1.0";
            status = "disabled";
            clocks = <&clkc 20>, <&clkc 37>;
            clock-names = "can_clk", "pclk";
            reg = <0xe0009000 0x1000>;
            interrupts = <0 51 4>;
            interrupt-parent = <&intc>;
            tx-fifo-depth = <0x40>;
            rx-fifo-depth = <0x40>;
        };

        gpio0: gpio@e000a000 {
            compatible = "xlnx,zynq-gpio-1.0";
            #gpio-cells = <2>;
            clocks = <&clkc 42>;
            gpio-controller;
            interrupt-controller;
            #interrupt-cells = <2>;
            interrupt-parent = <&intc>;
            interrupts = <0 20 4>;
            reg = <0xe000a000 0x1000>;
        };

        i2c0: i2c@e0004000 {
            compatible = "cdns,i2c-r1p10";
            status = "disabled";
            clocks