.align 5
vector_\name:
.if \correction
sub lr, lr, #\correction
.endif
@
@ Save r0, lr_<exception> (parent PC) and spsr_<exception>
@ (parent CPSR)
@
stmia sp, {r0, lr} @ save r0, lr
mrs lr, spsr
str lr, [sp, #8] @ save spsr
@
@ Prepare for SVC32 mode. IRQs remain disabled.
@
mrs r0, cpsr
eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
msr spsr_cxsf, r0
@
@ the branch table must immediately follow this code
@
and lr, lr, #0x0f
THUMB( adr r0, 1f )
THUMB( ldr lr, [r0, lr, lsl #2] )
mov r0, sp
ARM( ldr lr, [pc, lr, lsl #2] )
movs pc, lr @ branch to handler in SVC mode
ENDPROC(vector_\name)
/*
* Interrupt dispatcher
*/
vector_stub
irq, IRQ_MODE, 4
.long __irq_usr
@ 0 (USR_26 / USR_32)
.long __irq_invalid
@ 1 (FIQ_26 / FIQ_32)
.long __irq_invalid
@ 2 (IRQ_26 / IRQ_32)
.long __irq_svc
@ 3 (SVC_26 / SVC_32)
.long __irq_invalid
@ 4
.long __irq_invalid
@ 5
.long __irq_invalid
@ 6
.long __irq_invalid
@ 7
.long __irq_invalid
@ 8
.long __irq_invalid
@ 9
.long __irq_invalid
@ a
.long __irq_invalid
@ b
.long __irq_invalid
@ c
.long __irq_invalid
@ d
.long __irq_invalid
@ e
.long __irq_invalid
@ f