Recently, I noticed a new SOC: Quark. It sounds like the meaning as the name. A tiny CPU.. Okay, It should be named SOC ( System on Chip)
Abviously, It include a Memory Controller, A group of general I/O, SD interface, PCI-e..
Let me list some typical features :
SoC CPU Core Feature:
1) 400 MHZ maximum operating frequency....
2) Low power options to run at half or at quarter of maximum CPU frequency
3) 32-bit address bus, 32-bit data bus ( IA instruction sets)
4) 16 Kbyte shared instruction and dta L1 cache.
Memory Controller Features:
1) Single channel DDR3 memory cotnroller with ECC support
2) 16-bit data bus
3) Supports up to two ranks total(2GByte)
4) Supports DDR3 with 800 MT/s data rates (No faster, but enought )
5) x8 DRAM device data width
6) 1 Gbit, 2Gbit, and 4 Gibt DRAM device densities
7) Total memory size from 128 Mbyte to 2Gbyte.
8) Supports different physical mappings of bank addresses to optimize performance.
9) Out-of-order request processing to increase performance
10) Aggressive power management to reduce power consumption
11) Proactive page closing policies to close unused pages
12) Supports soldered down DRAM device
Embedded SDRAM Features:
Low Latency 512 Kbyte on-die embedded SRAM
COnfigurable to either overlay a 512 Kbyte block or overlay individual 4 Kbyte pages of system memory
ECC protected
Ethernet Features:
1) 10 and 100 Mbps data transfer rates with RMII interface to communicate iwth an external Fast Ethernet PHY
2) Full-duplex operation:
---- IEEE 802.3x flow control support
---- Optional forwarding of received pause control frames to the user application
3) Half-duplex operation:
---- CSMA/CD Protocol support
4) Flexible address filtering modes:
---- 64-bit Hash filter for multicast and unicast (DA) addresses
---- Option to pass all multicast addressed frames
---- Promiscuous mode to pass all frames without any filtering for network monitoring
---- Pass all incoming packets (as per filter) with a status report
5) Programmable frame length to support Standard Ethernet frames with size up to 1522 bytes
6) Enahanced Receive module for checking IPv4 hader checsum and TCP, UDP, or ICMP checksum encapsulated in IPv4 or IPv6 datagrams (Type2)
7) Support Ethernet frame timing stamping as described in IEEE 1588-2002 and IEEE 1588-2008. The 64-bit timestamps are given in the transmit or receive status of each fram.
USB Host Controller Features:
1) 2 host ports that support high-speed (480 Mbps), full-speed(12 Mbps), and low-speed(1.5Mbps) operation
2) EHCI and OHCI host controllers
USB2 Device Controller Features:
1) Single device port that supports high-speed (480 Mbps) and full-speed (12 Mbps) operation