Understanding RAM Timings

source: http://www.hardwaresecrets.com/printpage/Understanding-RAM-Timings/26   

By Gabriel Torres on May 17, 2011

Introduction

DDR, DDR2,and DDR3 memories are classified according to the maximum speed at whichthey can work, as well as their timings. Timings are numbers suchas 3-4-4-8, 5-5-5-15, 7-7-7-21, or 9-9-9-24, the lower the better. In thistutorial, we will explain exactly what each one of these numbersmean.

DDR, DDR2,and DDR3 memories follow the DDRxxx/PCyyyy classification. By the way, ifyou are interested in knowing the difference between DDR, DDR2, andDDR3 memories,read our tutorial onthis subject.

Thefirst number, xxx, indicates the maximum clock speed that the memory chipssupport. For instance, DDR400 memories work at 400 MHz at themost, DDR2-800 can work up to 800 MHz, and DDR3-1333 can work up to1,333 MHz. It is important to note that this is not the real clock speed of thememory. The real clock of the DDR, DDR2, and DDR3 memories is half ofthe labeled clock speed. Therefore DDR400 memories work at 200MHz, DDR2-800 memories work at 400 MHz, and DDR3-1333 memories workat 666 MHz.

Thesecond number indicates the maximum transfer rate that the memory reaches, inMB/s. DDR400 memories transfer data at 3,200 MB/s at the most, and hence theyare labeled as PC3200. DDR2-800 memories transfer data at 6,400 MB/s and theyare labeled as PC2-6400. And DDR3-1333 memories can transfer data at 10,664MB/s and they are labeled as PC3-10600 or PC3-10666. As you can see, we use thenumber “2” or “3” after “DDR” or “PC” to indicate that we are talking about aDDR2 or DDR3 memory, not DDR.

Thefirst classification, DDRxxx, is the standard used to classify memory chips,while the second classification, PCyyyy, is the standard used to classifymemory modules. In Figure 1, you can see a PC3-10666 memory module, which usesDDR3-1333 memory chips. Pay attention to the timings (7-7-7-18) and voltage(1.5 V).

Figure 1: A DDR3-1333/PC3-10666memory module

Themaximum transfer rate for a memory module can be calculated through thefollowing formula:

Maximum Theoretical Transfer Rate = clock x number of bits / 8

SinceDIMM modules transfer 64 bits at a time, “number of bits” will be 64. As 64 / 8equals 8, we can simplify this formula to:

Maximum Theoretical Transfer Rate = clock x 8

Ifthe memory module is installed on a system where the memory bus is running at alower clock rate, the maximum transfer rate the memory module will achieve willbe lower than its theoretical maximum transfer rate. Actually, this is a verycommon misjudgment.

Forexample, let’s say that you bought a pair of DDR3-2133/PC3-17000 memories. Eventhough they are labeled as DDR3-2133, they won’t run at 2,133 MHzautomatically on your system. This is the maximum clock rate they support, notthe clock rate at which they will be running. If you install it on a regular PCsystem supporting DDR3 memories, they will probably run at 1,333 MHz(DDR3-1333) – which the maximum DDR3 standard speed –, achieving a maximumtransfer rate of 10,664 MB/s (or 21,328 MB/s if they are running under dualchannel mode, read our tutorial on dualchannel to understand more about this subject). So, they won’tautomatically run at 2,133 MHz nor automatically achieve the 17,000 MB/stransfer rate.

So,why would someone buy these modules? Someone would buy them foroverclocking. Since the manufacturer guarantees that these modules will run upto 2,133 MHz, you know that you can raise the memory bus clock up to 1,066 MHzto achieve a higher performance with your system. However, your motherboardmust support this kind of overclocking (readour tutorial on memory overclocking for more details). Thus buying amemory module with a labeled clock rate higher than what your system supportsis useless if you are not going to overclock your system.

Forthe average user, that is everything you need to know about DDR,DDR2, and DDR3 memories. For the advanced user, there is yet anothercharacteristic: the temporization of the memory, a.k.a. timings or latency.Let’s talk about it.

Timings

Becauseof timings, two memory modules with the same theoretical maximum transfer ratecan achieve different performance levels. Why is this possible if both arerunning at the same clock rate?

Timingsmeasure the time the memory chip delays doing something internally. Here isan example. Consider the most famous parameter, which is called CASLatency (or CL or “access time”) that tells us how many clock cycles thememory module will delay in returning data requested by the CPU. A memorymodule with a CL 9 will delay nine clock cycles to deliver a requesteddata, whereas a memory module with a CL 7 will delay seven clockcycles to deliver it. While both modules may run at the same clock rate, thesecond one will be faster, as it will deliver data sooner than the first one.This issue is known as “latency.” As you can see in Figure 1, the moduleportrayed there has a CL of 7.

Thememory timings are given through a series of numbers; for instance, 4-4-4-8,5-5-5-15, 7-7-7-21, or 9-9-9-24. These numbers indicate the amount of clockcycles that it takes the memory to perform a certain operation. The smaller thenumber, the faster the memory. The memory module portrayed in Figure 1 has 7-7-7-18 timings, while the memory module portrayed in Figure 2 has 8-8-8-24 timings.

Figure 2: A DDR3-1600/PC3-12800memory module with 8-8-8-24 timings

Theoperations that these numbers indicate are the following: CL-tRCD-tRP-tRAS-CMD.To understand them, bear in mind that the memory is internally organized as amatrix, where the data are stored at the intersection of the lines and columns.

• CL: CAS Latency. The time it takes between a command having been sent to the memory and when it begins to reply to it. It is the time it takes between the processor asking for some data from the memory and then returning it.
• tRCD: RAS to CAS Delay. The time it takes between the activation of the line (RAS) and the column (CAS) where the data are stored in the matrix.
• tRP: RAS Precharge. The time it takes between disabling the access to a line of data and the beginning of the access to another line of data.
• tRAS: Active to Precharge Delay. How long the memory has to wait until the next access to the memory can be initiated.
• CMD: Command Rate. The time it takes between the memory chip having been activated and when the first command may be sent to the memory. Sometimes this value is not announced. It usually is T1 (1 clock cycle) or T2 (2 clock cycles).

Usually,you have two options: to configure your PC to use the memory standard timings, usually by setting memory configuration to “Auto” on the motherboard setup; or to manually configure your PC to use lower memory timings, which may increase the performance of your system. Notice that not allmotherboards allow you to change the memory timings. Also, some motherboards may not be able to run at very low timings, and they may configure your memory module to run at a higher timing setting because of this.

Figure 3: Configuration of memorytimings at the motherboard setup

Whenoverclocking your memory, you may need to increase the memory timings in orderto make the system run in a stable manner. Here is where something veryinteresting happens. Due to the increased timings, the memory may achieve alower performance, even though it is now configured to run at a higher clockrate, due to the latency that was introduced.

Thatis another advantage of memory modules sold specifically for overclocking. Themanufacturer, besides guaranteeing that your memory module will achieve thelabeled clock rate, also guarantees that you will be able to keep the labeledtimings up to the labeled clock.

Forexample, even though you may achieve 1,600 MHz (800 MHz x2)with DDR3-1333/PC3-10600 modules, on these modules it may be necessary toincrease the memory timings, while on DDR3-1600/PC3-12800 ones themanufacturer guarantees that you will be able to achieve 1,600 MHz keepingthe labeled timings.

Now we are going a step further as we will explain in detail each one of the memorytiming parameters.

CAS Latency (CL)

Aspreviously mentioned, CAS Latency (CL) is the best known memory parameter.It tells us how many clock cycles the memory will delay toreturn requested data. A memory with CL = 7 will delay sevenclock cycles to deliver data, while a memory with CL = 9 willdelay nine clock cycles to perform the same operation. Thus, for twomemory modules running at the same clock rate, the one with the lowest CL willbe faster.

Noticethat the clock rate here is the real clock rate under which the memory moduleis running – i.e., half the rated clock rate. As DDR, DDR2, and DDR3memories can deliver two data per clock cycle, they are rated with double theirreal clock rate.

InFigure 4, you can see how CL works. We gave two examples, a memory module withCL = 7 and a memory module with CL = 9. The command in blue would be a“read” command.

Figure 4: CAS Latency (CL)

Amemory with CL = 7 will provide a 22.2% improvement on memory latency overa memory with CL = 9, considering that both are running at the same clock rate.

Youcan even calculate the time the memory delays until it starts delivering data.The period of each clock cycle can be easily calculated through the formula:

T = 1 / f

Thus,the period of each clock cycle of a DDR3-1333 memory running at 1333 MHz(666.66 MHz clock) would be 1.5 ns (ns = nanosecond; 1 ns = 0.000000001 s).Keep in mind that you need to use the real clock rate, which is half of thelabeled clock rate. So, this DDR3-1333 memory would delay 10.5 ns to startdelivering data if it had CL =7, or 13.5 ns if it had CL = 9, for example.

SDRAM,DDR, DDR2, and DDR3 memories implement burst mode, where data storedin the next addresses can exit the memory at only one clock cycle. So, whilethe first data would delay CL clock cycles to exit the memory, the next datawould be delivered right after the prior data that has just come out from thememory, not having to wait for another CL cycle. Also, DDR, DDR2, and DDR3memories deliver two data per clock cycle, and that is why they are labeled ashaving twice their real clock rate.

RAS to CAS Delay (tRCD)

Eachmemory chip is organized internally as a matrix. At the intersection of eachrow and column we have a small capacitor that is in charge of storing a “0” ora “1” – the data. Inside the memory, the process of accessing the stored datais accomplished by first activating the row then the column where it islocated. This activation is done by two control signals called RAS (Row AddressStrobe) and CAS (Column Address Strobe). The less time there is between thesetwo signals the better, as the data will be read sooner. RAS to CAS Delay ortRCD measures this time. In Figure 5 we illustrate this, showing a memory withtRCD = 3.

Figure 5: RAS to CAS Delay (tRCD)

Asyou can see, RAS to CAS Delay is also the number of clock cycles taken betweenthe “Active” command and a “read” or “write” command.

Aswith CAS Latency, RAS to CAS Delay works with the memory real clock (which ishalf of the labeled clock). The lower this parameter, the faster thememory will be, as it will start reading or writing data earlier.

RAS Precharge (tRP)

Afterdata is gathered from the memory, a command called Precharge needs to beissued, closing the memory row that was being used and allowing a new row to beactivated. RAS Precharge time (tRP) is the time taken between when thePrecharge command and the next Active command can be issued. As we learned fromthe previous page, the Active command starts a read or write cycle.

Figure 6: RAS Precharge (tRP)

InFigure 6, we are giving an example of a memory with tRP = 3.

As withthe other parameters, RAS Precharge works with the memory real clock (which ishalf of the labeled clock). The lower this parameter, the faster thememory will be, as it will issue the Active command earlier.

Addingeverything we’ve seen, the time elapsed between issuing the Precharge commandand actually getting the data will be tRP + tRCD + CL.

Other Parameters

Let’stake a better look at the other two parameters, Active to Precharge Delay(tRAS) and Command Rate (CMD). As with the other parameters, these twoparameters work with the memory real clock (which is half of the memory labeledclock). The lower these parameters, the faster the memory will be.

• Active to Precharge Delay (tRAS): After an Active command is issued, another Precharge command cannot be issued until tRAS has elapsed. So, this parameter limits when the memory can start reading (or writing) a different row.
• Command Rate (CMD): It is the time taken by the memory chip from being activated (through its CS – Chip Select – pin) and when any command can be issued to the memory. This parameter carries the letter “T” with it. Possible values are 1T or 2T, meaning one clock cycle or two clock cycles, respectively.