UE veriog 语法设置

最新推荐文章于 2025-06-19 14:08:56 发布

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最新推荐文章于 2025-06-19 14:08:56 发布

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本文链接：https://blog.youkuaiyun.com/timeless_2014/article/details/84928986

转载注明：https://blog.youkuaiyun.com/timeless_2014/article/details/84928986

1、将下面Verilog高亮显示定义加入UE安装目录下的wordfile文件里：
/L14"Verilog 1364-2001" Line Comment = // Block Comment On = /* Block Comment Off = */ Block Comment On Alt = (* Block Comment Off Alt = *) String Chars = " File Extensions = V VL VMD
/Delimiters = ~!@%^&*()-+=|\/{}[]:;"<> ,
/Function String = "%[ ^t]++^(config[ ^t^p]+[a-zA-Z0-9_]+^)"
/Function String 1 = "%[ ^t]++^(module[ ^t^p]+[a-zA-Z0-9_]+^)[ ^t^p]++[(;#]"
/Function String 2 = "%[ ^t]++^(task[ ^t^p]+[~(;]+^)[ ^t^p]++[(;#]"
/Function String 3 = "%[ ^t]++^(function[ ^t^p]+[~(;]+^)[ ^t^p]++[(;#]"
/Function String 4 = "%[ ^t]++^(primitive[ ^t^p]+[~(;]+^)[ ^t^p]++[(;#]"
/Function String 5 = "begin[ ^t^p]++^(:[ ^t^p]++[a-zA-Z0-9_]+^)"
/Indent Strings = "begin" "case" "fork" "specify" "table" "config"
/Unindent Strings = "end" "endcase" "join" "endspecify" "endtable" "endconfig"
/Open Fold Strings = "module" "task" "function" "generate" "primitive" "begin" "case" "fork" "specify" "table" "config" "`ifdef"
/Close Fold Strings = "endmodule" "endtask" "endfunction" "endgenerate"