ANIS_VITA标准概述

VITA(VMEbus International Trade Association)标准是嵌入式系统领域广泛采用的开放式架构规范,主要用于军事、航空航天、工业自动化等高可靠性场景。该标准系列涵盖硬件、软件和通信协议,强调模块化、可扩展性和实时性,核心成员包括VME64x、VPX、VXS等。

VITA标准的发展历程

VITA组织成立于1981年,最初围绕VME总线(Versa Module Eurocard)制定标准。随着技术进步,VME逐步演化为VPX(VITA 46/48)和OpenVPX(VITA 65),支持高速串行通信(如PCIe、以太网)。2010年后,VITA 49(VITA Radio Transport)和VITA 57(FPGA夹层卡)进一步扩展了应用场景。

核心标准分类

VME/VME64x:传统并行总线架构,带宽达320MB/s,适用于 legacy 系统升级。
VPX (VITA 46):采用高速串行交换结构,支持PCIe、SRIO等协议,带宽提升至10Gbps/通道。
OpenVPX (VITA 65):定义VPX的互操作性规范,明确模块尺寸、背板拓扑和冷却方案。
VITA 49:专注于数字化射频信号传输(如SDR),支持JESD204B标准。

技术特点

  • 模块化设计:3U/6U尺寸规范,支持热插拔和冗余配置。
  • 高带宽:VPX背板支持多路PCIe Gen3/Gen4,满足大数据吞吐需求。
  • 强固性:符合MIL-STD-810抗冲击、振动标准,适用恶劣环境。

应用场景

  • 国防电子:雷达、电子战设备的实时信号处理。
  • 航空航天:星载计算机和飞行控制系统的冗余架构。
  • 医疗影像:高分辨率CT/MRI设备的模块化数据处理。

未来趋势

VITA标准持续集成新兴技术,如VITA 78(SpaceVPX)针对航天应用优化,VITA 90(光学互连)探索光背板解决方案。边缘计算和AI的兴起推动VPX与AI加速器(如GPU/FPGA)的深度融合。

Abstract This standard describes VITA 46.0 Advanced Module Format for VMEbus systems, an evolutionary step forward for the provision of high-speed interconnects in harsh-environment applications. Foreword VME has been the de-facto bus standard for Commercial off the Shelf ( COTS ) Circuit Card Assemblies since the 1980’s. VME boards have proven to be remarkably capable of evolving to support newer technologies with innovations such as VME Subsystem Bus, PCI Mezzanine Cards (PMC’s) and VME320. However, advances in technologies, appearing particularly in interconnects, have demonstrated the need for an advance in system development. This advance needs to accommodate high speed interconnect, particularly serial interconnects, and higher power delivery in concert with better heat removal. This draft standard addresses these needs in the context of IEEE 1101 form factor modules. Other specifications may address alternate outlines, such as VITA-48 (Draft). Because electronics miniaturization is driving the plug-in module I/O count, most system interconnects will need:  Multi-gigabit differential technology  Core computing cluster switched fabrics  Serial RapidIO, PCI Express, Advanced Switching Interconnect  Sufficient ports to enable distributed switching or centralized switching The plethora of high-speed interfaces available for tomorrow’s plug-in modules:  Network interfaces (Fibre Channel, 10 GbE XAUI, Infiniband…,)  Digital video (TMDS, PanelLink, OpenLDI…)  Mass storage interface (Fibre Channel, Serial ATA…,)  FPGA-based inter-board connections (e.g. Xilinx RocketIO)  Custom sensor interfaces VITA 46 provides an evolutionary roadmap for VME users:  To leverage the broad spectrum of high-speed interconnect technologies  Backward compatibility with VME bus electrical, software and selected mechanicals  Enables heterogeneous architectures which preserve existing investments in COTS-based systems  Addresses both 3U and 6U form factors with commonality  Harsh environment fit ‘designed-in’ up front in the standard  Rugged air or conduction-cooled form factors  High value placed on rear-panel I/O  High-speed connector survivability/compliance
import numpy as np import matplotlib.pyplot as plt from matplotlib.ticker import PercentFormatter path1='/media/zekun/Software/pictures/anis_yn_final/lvz-w' path2='/media/zekun/Software/pictures/anis_yn_final/lvz1-self' png_folder='/media/zekun/Software/fenglin_niu/yn-pic/percent-lvz1.png' # 打开文件并读取所有行 with open(path1, 'r') as f: lines = f.readlines() # 获取第一列所有数字并转换为浮点数 nums1 = [float(line.split()[1]) for line in lines] #average = sum(nums) / len(nums) # 打开文件并读取所有行 with open(path2, 'r') as f: lines = f.readlines() # 获取第一列所有数字并转换为浮点数 nums2 = [float(line.split()[11]) for line in lines] #average = sum(nums) / len(nums) # 定义统一的分箱边界 bins = [0, 0.2, 0.4, 0.6, 0.8, 1, 1.2, 1.4] weights1 = np.ones(len(nums1)) / len(nums1) # 计算权重 weights2 = np.ones(len(nums2)) / len(nums2) # 计算权重 # 绘制直方图 plt.figure(figsize=(4.5, 4)) plt.hist(nums1, bins=bins, facecolor="dodgerblue", alpha=0.9, weights=weights1) counts, bin_edges = np.histogram(nums2, bins=bins, weights=weights2) for i in range(len(counts)): left = bin_edges[i] right = bin_edges[i+1] height = counts[i] if height > 0: plt.plot([left, right], [height, height], color="red", linewidth=2) plt.plot([left, left], [0, height], color="red", linewidth=2) plt.plot([right, right], [height, 0], color="red", linewidth=2) # 格式化纵轴为百分比 plt.gca().yaxis.set_major_formatter(PercentFormatter(1)) plt.ylim(0, 0.7) # 强制设置纵轴范围0-70% # 设置坐标轴 #plt.yticks([]) # 隐藏纵轴 plt.xticks(np.arange(0, 1.4, 0.6)) # +0.4确保包含最大值 plt.yticks(np.arange(0, 0.71, 0.1)) plt.savefig(png_folder, format="png", transparent=True, dpi=1000) plt.show() 现在在纵轴上我只想标注30%和60%两处
03-29
这...出什么问题了胚胎图像预处理量化报告 生成时间: 2025-10-10 02:49:05 处理图像数: 4 各阶段质量指标(均值 ± 标准差): 1_original: 平均强度: 175.196 ± 3.03 噪声水平(标准差): 35.592 ± 9.853 对比度: 0.204 ± 0.059 信息熵: 6.5 ± 0.7739999890327454 信噪比: 5.368 ± 2.15 2_anis_diff: 平均强度: 175.196 ± 3.03 噪声水平(标准差): 35.592 ± 9.853 对比度: 0.204 ± 0.059 信息熵: 6.5 ± 0.7739999890327454 信噪比: 5.368 ± 2.15 3_bilateral: 平均强度: 175.19 ± 3.039 噪声水平(标准差): 35.406 ± 9.791 对比度: 0.203 ± 0.058 信息熵: 6.466000080108643 ± 0.7889999747276306 信噪比: 5.395 ± 2.157 4_poisson_denoise: 平均强度: 175.024 ± 3.1 噪声水平(标准差): 35.193 ± 9.664 对比度: 0.202 ± 0.058 信息熵: 5.874000072479248 ± 0.972000002861023 信噪比: 5.414 ± 2.143 5_normalized: 平均强度: 188.704 ± 5.543 噪声水平(标准差): 52.822 ± 0.552 对比度: 0.28 ± 0.007 信息熵: 4.935999870300293 ± 0.9210000038146973 信噪比: 3.572 ± 0.094 6_clahe: 平均强度: 172.323 ± 4.789 噪声水平(标准差): 62.763 ± 5.874 对比度: 0.365 ± 0.043 信息熵: 6.939000129699707 ± 0.2370000034570694 信噪比: 2.769 ± 0.342 7_sharpened: 平均强度: 172.323 ± 4.788 噪声水平(标准差): 62.764 ± 5.874 对比度: 0.365 ± 0.043 信息熵: 6.939000129699707 ± 0.2370000034570694 信噪比: 2.769 ± 0.342 8_final: 平均强度: 172.324 ± 4.787 噪声水平(标准差): 62.526 ± 5.828 对比度: 0.364 ± 0.042 信息熵: 6.998000144958496 ± 0.24400000274181366 信噪比: 2.78 ± 0.34
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