一个全面获取Intel CPUID的代码

最新推荐文章于 2025-06-09 15:15:41 发布
原创最新推荐文章于 2025-06-09 15:15:41 发布 · 4.8k 阅读
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CC 4.0 BY-SA版权
文章标签：
#cache #byte #descriptor #mobile #extension #debugging
本文介绍了通过CPUID指令获取CPU的详细信息，包括品牌、型号、缓存类型、特征信息、管理功能等，并展示了如何解析和展示这些信息。
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// 主函数：CString GetCPUIDString()
// Copyright (C) shangweixiao 2011

////////////////////////////////////////////////////////
class CSortStringArray:public CStringArray
{
public:
	void Sort();
private:
	BOOL CompareAndSwap(int pos);
};

void CSortStringArray::Sort()
{
	BOOL bNotDone = TRUE;

	while (bNotDone)
	{
		bNotDone = FALSE;
		for(int pos = 0;pos < GetUpperBound();pos++)
			bNotDone |= CompareAndSwap(pos);
	}
}
BOOL CSortStringArray::CompareAndSwap(int pos)
{
	CString temp;
	int posFirst = pos;
	int posNext = pos + 1;

	if (GetAt(posFirst).CompareNoCase(GetAt(posNext)) > 0)
	{
		temp = GetAt(posFirst);
		SetAt(posFirst, GetAt(posNext));
		SetAt(posNext, temp);
		return TRUE;

	}
	return FALSE;
}
////////////////////////////////////////////////////////////

void GetCPUID(UINT32 Operand, UINT32 Value[8])
{
	UINT32 ulS1,ulS2,ulS3,ulS4;

	__asm
	{
			mov eax,Operand
			xor ebx,ebx
			xor ecx,ecx
			xor edx,edx
			cpuid
			mov ulS1,eax
			mov ulS2,ebx
			mov ulS3,ecx
			mov ulS4,edx
	}

	Value[0] = ulS1;
	Value[1] = ulS2;
	Value[2] = ulS3;
	Value[3] = ulS4;
}

void GetCPUID2(UINT32 Operand,UINT32 Operand2,UINT32 Value[8])
{
	UINT32 ulS1,ulS2,ulS3,ulS4;

	__asm
	{
			mov eax,Operand
			mov ecx,Operand2
			xor ebx,ebx
			xor edx,edx
			cpuid
			mov ulS1,eax
			mov ulS2,ebx
			mov ulS3,ecx
			mov ulS4,edx
	}

	Value[0] = ulS1;
	Value[1] = ulS2;
	Value[2] = ulS3;
	Value[3] = ulS4;
}

#define SWAP_VALUE(x,y) {x=x^y;y=x^y;x=x^y;}
#define SET_BIT(v,i) ((v) |= (0x1 << (i)))
#define TEST_BIT(v,i) (!!((v) & (0x1 << (i))))
int GetBitsValue(UINT32 org,UINT32 start,UINT32 end)
{
	UINT32 i,mask=0;

	for(i=start;i<=end;i++)
	{
		SET_BIT(mask,i);
	}
	return (org & mask)>>start;
}

char *BrandString[]={
	"None",
	"Intel(R) Celeron(R) processor",
	"Intel(R) Pentium(R) III processor",
	"Intel(R) Pentium(R) III Xeon(R) processor",
	"Intel(R) Pentium(R) III processor",
	"Mobile Intel(R) Pentium(R) III processor-M",
	"Mobile Intel(R) Celeron(R) processor",
	"Intel(R) Pentium(R) 4 processor",
	"Intel(R) Pentium(R) 4 processor",
	"Intel(R) Celeron(R) processor",
	"Intel(R) Xeon(R) processor",
	"Intel(R) Xeon(R) processor MP",
	"Mobile Intel(R) Pentium(R) 4 processor-M",
	"Mobile Intel(R) Celeron(R) processor",
	"Mobile Genuine Intel(R) processor",
	"Intel(R) Celeron(R) M processor",
	"Mobile Intel(R) Celeron(R) processor",
	"Intel(R) Celeron(R) processor",
	"Mobile Genuine Intel(R) processor",
	"Intel(R) Pentium(R) M processor",
	"Mobile Intel(R) Celeron(R) processor"
};
char *Leaf_2_Descriptors[]={""
/*00*/ "", //"Null descriptor, this byte contains no information",
/*01*/ "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries",
/*02*/ "Instruction TLB: 4 MByte pages, fully associative, 2 entries",
/*03*/ "Data TLB: 4 KByte pages, 4-way set associative, 64 entries",
/*04*/ "Data TLB: 4 MByte pages, 4-way set associative, 8 entries",
/*05*/ "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries",
/*06*/ "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size",
/*07*/ "",
/*08*/ "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size",
/*09*/ "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size",
/*0A*/ "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size",
/*0B*/ "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries",
/*0C*/ "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size",
/*0D*/ "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size",
/*0E*/ "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size",
/*0F*/ "",
/*10*/ "",
/*11*/ "",
/*12*/ "",
/*13*/ "",
/*14*/ "",
/*15*/ "",
/*16*/ "",
/*17*/ "",
/*18*/ "",
/*19*/ "",
/*1A*/ "",
/*1B*/ "",
/*1C*/ "",
/*1D*/ "",
/*1E*/ "",
/*1F*/ "",
/*20*/ "",
/*21*/ "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size",
/*22*/ "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector",
/*23*/ "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector",
/*24*/ "",
/*25*/ "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector",
/*26*/ "",
/*27*/ "",
/*28*/ "",
/*29*/ "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector",
/*2A*/ "",
/*2B*/ "",
/*2C*/ "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size",
/*2D*/ "",
/*2E*/ "",
/*2F*/ "",
/*30*/ "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size",
/*31*/ "",
/*32*/ "",
/*33*/ "",
/*34*/ "",
/*35*/ "",
/*36*/ "",
/*37*/ "",
/*38*/ "",
/*39*/ "",
/*3A*/ "",
/*3B*/ "",
/*3C*/ "",
/*3D*/ "",
/*3E*/ "",
/*3F*/ "",
/*40*/ "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rdlevel cache",
/*41*/ "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size",
/*42*/ "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size",
/*43*/ "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size",
/*44*/ "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size",
/*45*/ "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size",
/*46*/ "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size",
/*47*/ "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size",
/*48*/ "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size",
/*49*/ "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H);",
/*4A*/ "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size",
/*4B*/ "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size",
/*4C*/ "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size",
/*4D*/ "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size",
/*4E*/ "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size",
/*4F*/ "Instruction TLB: 4 KByte pages, 32 entries",
/*50*/ "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries",
/*51*/ "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries",
/*52*/ "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries",
/*53*/ "",
/*54*/ "",
/*55*/ "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries",
/*56*/ "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries",
/*57*/ "Data TLB0: 4 KByte pages, 4-way associative, 16 entries",
/*58*/ "",
/*59*/ "Data TLB0: 4 KByte pages, fully associative, 16 entries",
/*5A*/ "Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries",
/*5B*/ "Data TLB: 4 KByte and 4 MByte pages, 64 entries",
/*5C*/ "Data TLB: 4 KByte and 4 MByte pages,128 entries",
/*5D*/ "Data TLB: 4 KByte and 4 MByte pages,256 entries",
/*5E*/ "",
/*5F*/ "",
/*60*/ "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size",
/*61*/ "",
/*62*/ "",
/*63*/ "",
/*64*/ "",
/*65*/ "",
/*66*/ "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size",
/*67*/ "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size",
/*68*/ "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size",
/*69*/ "",
/*6A*/ "",
/*6B*/ "",
/*6C*/ "",
/*6D*/ "",
/*6E*/ "",
/*6F*/ "",
/*70*/ "Trace cache: 12 K-uop, 8-way set associative",
/*71*/ "Trace cache: 16 K-uop, 8-way set associative",
/*72*/ "Trace cache: 32 K-uop, 8-way set associative",
/*73*/ "",
/*74*/ "",
/*75*/ "",
/*76*/ "",
/*77*/ "",
/*78*/ "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size",
/*79*/ "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector",
/*7A*/ "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector",
/*7B*/ "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector",
/*7C*/ "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector",
/*7D*/ "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size",
/*7E*/ "",
/*7F*/ "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size",
/*80*/ "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size",
/*81*/ "",
/*82*/ "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size",
/*83*/ "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size",
/*84*/ "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size",
/*85*/ "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size",
/*86*/ "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size",
/*87*/ "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size",
/*88*/ "",
/*89*/ "",
/*8A*/ "",
/*8B*/ "",
/*8C*/ "",
/*8D*/ "",
/*8E*/ "",
/*8F*/ "",
/*90*/ "",
/*91*/ "",
/*92*/ "",
/*93*/ "",
/*94*/ "",
/*95*/ "",
/*96*/ "",
/*97*/ "",
/*98*/ "",
/*99*/ "",
/*9A*/ "",
/*9B*/ "",
/*9C*/ "",
/*9D*/ "",
/*9E*/ "",
/*9F*/ "",
/*A0*/ "",
/*A1*/ "",
/*A2*/ "",
/*A3*/ "",
/*A4*/ "",
/*A5*/ "",
/*A6*/ "",
/*A7*/ "",
/*A8*/ "",
/*A9*/ "",
/*AA*/ "",
/*AB*/ "",
/*AC*/ "",
/*AD*/ "",
/*AE*/ "",
/*AF*/ "",
/*B0*/ "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries",
/*B1*/ "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries",
/*B2*/ "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries",
/*B3*/ "Data TLB: 4 KByte pages, 4-way set associative, 128 entries",
/*B4*/ "Data TLB1: 4 KByte pages, 4-way associative, 256 entries",
/*B5*/ "",
/*B6*/ "",
/*B7*/ "",
/*B8*/ "",
/*B9*/ "",
/*BA*/ "Data TLB1: 4 KByte pages, 4-way associative, 64 entries",
/*BB*/ "",
/*BC*/ "",
/*BD*/ "",
/*BE*/ "",
/*BF*/ "",
/*C0*/ "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries",
/*C1*/ "",
/*C2*/ "",
/*C3*/ "",
/*C4*/ "",
/*C5*/ "",
/*C6*/ "",
/*C7*/ "",
/*C8*/ "",
/*C9*/ "",
/*CA*/ "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries",
/*CB*/ "",
/*CC*/ "",
/*CD*/ "",
/*CE*/ "",
/*CF*/ "",
/*D0*/ "",
/*D1*/ "",
/*D2*/ "",
/*D3*/ "",
/*D4*/ "",
/*D5*/ "",
/*D6*/ "",
/*D7*/ "",
/*D8*/ "",
/*D9*/ "",
/*DA*/ "",
/*DB*/ "",
/*DC*/ "",
/*DD*/ "",
/*DE*/ "",
/*DF*/ "",
/*E0*/ "",
/*E1*/ "",
/*E2*/ "",
/*E3*/ "",
/*E4*/ "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size",
/*E5*/ "",
/*E6*/ "",
/*E7*/ "",
/*E8*/ "",
/*E9*/ "",
/*EA*/ "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size",
/*EB*/ "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size",
/*EC*/ "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size",
/*ED*/ "",
/*EE*/ "",
/*EF*/ "",
/*F0*/ "64-Byte prefetching",
/*F1*/ "128-Byte prefetching",
/*F2*/ "",
/*F3*/ "",
/*F4*/ "",
/*F5*/ "",
/*F6*/ "",
/*F7*/ "",
/*F8*/ "",
/*F9*/ "",
/*FA*/ "",
/*FB*/ "",
/*FC*/ "",
/*FD*/ "",
/*FE*/ "",
/*FF*/ "CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters",
};

char *Feature_Information1[]={
	"SSE3","PCLMULQDQ",
	"DTES64 64-bit DS Area",
	"MONITOR MONITOR/MWAIT",
	"DS-CPL CPL Qualified Debug Store",
	"VMX Virtual Machine Extensions",
	"SMX Safer Mode Extensions",
	"EST Enhanced Intel SpeedStep technology",
	"TM2 Thermal Monitor 2",
	"SSSE3",
	"CNXT-ID L1 Context ID",
	"",
	"FMA",
	"CMPXCHG16B CMPXCHG16B Available",
	"xTPR Update Control",
	"PDCM Perfmon and Debug Capability",
	"",
	"PCID Process-context identifiers",
	"DCA",
	"SSE4.1",
	"SSE4.2",
	"x2APIC",
	"MOVBE",
	"MOVBE",
	"TSC-Deadline",
	"AESNI",
	"XSAVE",
	"OSXSAVE",
	"AVX",
	"",
	"",
	"",
};
char *Feature_Information2[]={
	"FPU",
	"VME Virtual 8086 Mode Enhancements",
	"DE Debugging Extensions",
	"PSE Page Size Extension",
	"TSC Time Stamp Counter",
	"MSR Model Specific Registers RDMSR and WRMSR Instructions",
	"PAE",
	"MCE Machine Check Exception",
	"CX8 CMPXCHG8B Instruction",
	"APIC",
	"",
	"SEP SYSENTER and SYSEXIT Instructions",
	"MTRR Memory Type Range Registers",
	"PGE Page Global Bit",
	"MCA Machine Check Architecture",
	"CMOV Conditional Move Instructions",
	"PAT Page Attribute Table",
	"PSE-36 36-Bit Page Size Extension",
	"PSN Processor Serial Number",
	"CLFSH CLFLUSH Instruction",
	"",
	"DS Debug Store",
	"ACPI Thermal Monitor and Software Controlled Clock Facilities",
	"MMX",
	"FXSR FXSAVE and FXRSTOR Instructions",
	"SSE",
	"SSE2",
	"SS",
	"HTT Multi-Threading",
	"TM Thermal Monitor",
	"",
	"PBE Pending Break Enable",
};

char *Cache_Type[]={
	"Null - No more caches",
	"Data Cache",
	"Instruction Cache",
	"Unified Cache",
	"","","","","","","","","","","","","","","","","","","","","","","","","","","","",
};

char *Power_Management[]={
	"Digital temperature sensor is supported",
	"Intel Turbo Boost Technology Available",
	"ARAT APIC-Timer-always-running",
	"",
	"PLN Power limit notification controls",
	"ECMD Clock modulation duty cycle extension",
	"PTM Package thermal management"
};

CString GetCPUIDString()
{
	CString OutputStr,OrgStr;
	UINT32 i,j,Value[8],MaxOperand;
	CSortStringArray sortArray;

	MaxOperand = 0;
	OutputStr.Empty();
	for(i=0;i<=MaxOperand;i++)
	{
		if(i==7 || i==8 || i==0x0c)
		{
			continue;
		}
		memset(Value,0,sizeof(Value));
		GetCPUID(i,Value);
		OrgStr.Format("EAX Operand 0x%X,0x%08X-0x%08X-0x%08X-0x%08X\r\n",i,Value[0],Value[1],Value[2],Value[3]);
		OutputStr.Append(OrgStr);
		switch(i)
		{
			case 0:
				MaxOperand = Value[0];
				SWAP_VALUE(Value[2],Value[3]);
				OrgStr.Format("Vendor:%s\r\n",(char*)(&Value[1]));
				OutputStr.Append(OrgStr);
				OutputStr.Append("\r\n");
				break;
			case 1:
				OrgStr.Format("Extended Family ID:0x%X, Extended Model ID:0x%X, Family ID:0x%X, Model:0x%X, Stepping ID:0x%X\r\n",
					GetBitsValue(Value[0],20,27),GetBitsValue(Value[0],16,19),GetBitsValue(Value[0],8,11),
					GetBitsValue(Value[0],4,7),GetBitsValue(Value[0],0,3));
				OutputStr.Append(OrgStr);
				
				OrgStr.Format("Brand:%s, CLFLUSH line size:0x%X, Maximum number of addressable IDs:0x%X, Initial APIC ID: 0x%X\r\n",
					BrandString[GetBitsValue(Value[1],0,7)],GetBitsValue(Value[1],8,15),GetBitsValue(Value[1],24,31));
				OutputStr.Append(OrgStr);
				
				sortArray.RemoveAll();
				OrgStr.Empty();
				OutputStr.Append("Feature Information:");
				for(j=0;j<32;j++)
				{
					if(j==11 || j==16 || j==29 || j==30)
					{
						continue;
					}
					if(TEST_BIT(Value[2],j))
					{
						OrgStr.Format("%s,",Feature_Information1[j]);
						if(OrgStr.GetLength()<1)
						{
							continue;
						}
						sortArray.Add(OrgStr);
					}
				}

				for(j=0;j<32;j++)
				{
					if(j==10 || j==20 || j==30)
					{
						continue;
					}
					if(TEST_BIT(Value[3],j))
					{
						OrgStr.Format("%s,",Feature_Information2[j]);
						if(OrgStr.GetLength()<1)
						{
							continue;
						}
						sortArray.Add(OrgStr);
					}
				}

				sortArray.Sort();
				for(j=0;j<=sortArray.GetUpperBound();j++)
				{
					if(sortArray[j].GetLength()<1)
					{
						continue;
					}
					OutputStr.Append(sortArray[j]);
					if(j && 0==j%10)
					{
						OutputStr.Append("\r\n");
					}
				}
				OutputStr.Append("\r\n");
				OutputStr.Append("\r\n");
				break;
			case 2:
				sortArray.RemoveAll();
				if(!TEST_BIT(Value[0],31))
				{
					OrgStr.Format("%s",Leaf_2_Descriptors[GetBitsValue(Value[0],24,31)]);
					sortArray.Add(OrgStr);
					OrgStr.Format("%s",Leaf_2_Descriptors[GetBitsValue(Value[0],16,23)]);
					sortArray.Add(OrgStr);
					OrgStr.Format("%s",Leaf_2_Descriptors[GetBitsValue(Value[0],8,15)]);
					sortArray.Add(OrgStr);
				}


				if(!TEST_BIT(Value[1],31))
				{
					OrgStr.Format("%s",Leaf_2_Descriptors[GetBitsValue(Value[1],24,31)]);
					sortArray.Add(OrgStr);
					OrgStr.Format("%s",Leaf_2_Descriptors[GetBitsValue(Value[1],16,23)]);
					sortArray.Add(OrgStr);
					OrgStr.Format("%s",Leaf_2_Descriptors[GetBitsValue(Value[1],8,15)]);
					sortArray.Add(OrgStr);
					OrgStr.Format("%s",Leaf_2_Descriptors[GetBitsValue(Value[1],0,7)]);
					sortArray.Add(OrgStr);
				}

				if(!TEST_BIT(Value[2],31))
				{
					OrgStr.Format("%s",Leaf_2_Descriptors[GetBitsValue(Value[2],24,31)]);
					sortArray.Add(OrgStr);
					OrgStr.Format("%s",Leaf_2_Descriptors[GetBitsValue(Value[2],16,23)]);
					sortArray.Add(OrgStr);
					OrgStr.Format("%s",Leaf_2_Descriptors[GetBitsValue(Value[2],8,15)]);
					sortArray.Add(OrgStr);
					OrgStr.Format("%s",Leaf_2_Descriptors[GetBitsValue(Value[2],0,7)]);
					sortArray.Add(OrgStr);
				}


				if(!TEST_BIT(Value[3],31))
				{
					OrgStr.Format("%s",Leaf_2_Descriptors[GetBitsValue(Value[3],24,31)]);
					sortArray.Add(OrgStr);
					OrgStr.Format("%s",Leaf_2_Descriptors[GetBitsValue(Value[3],16,23)]);
					sortArray.Add(OrgStr);
					OrgStr.Format("%s",Leaf_2_Descriptors[GetBitsValue(Value[3],8,15)]);
					sortArray.Add(OrgStr);
					OrgStr.Format("%s",Leaf_2_Descriptors[GetBitsValue(Value[3],0,7)]);
					sortArray.Add(OrgStr);
				}

				sortArray.Sort();
				for(j=0;j<=sortArray.GetUpperBound();j++)
				{
					if(sortArray[j].GetLength()<1)
					{
						continue;
					}
					OutputStr.Append(sortArray[j]);
					OutputStr.Append("\r\n");
				}
				OutputStr.Append("\r\n");
				break;
			case 3:
				OrgStr.Format("processor serial number:0x%08X-0x%08X-0x%08X-0x%08X\r\n",Value[0],Value[1],Value[2],Value[3]);
				OutputStr.Append(OrgStr);
				OutputStr.Append("\r\n");
				break;
			case 4:
				GetCPUID2(4,0,Value);
				OrgStr.Format("Cache Type:%s,Cache Level:%d,Ways of associativity:%d,Cache Size:%dKB\r\n",
					Cache_Type[GetBitsValue(Value[0],0,4)],GetBitsValue(Value[0],5,7),GetBitsValue(Value[1],22,31),
					((GetBitsValue(Value[1],22,31)+1)*(GetBitsValue(Value[1],12,21)+1)*(GetBitsValue(Value[1],0,11)+1)*(Value[2]+1))>>10);
				OutputStr.Append(OrgStr);
				GetCPUID2(4,1,Value);
				OrgStr.Format("Cache Type:%s,Cache Level:%d,Ways of associativity:%d,Cache Size:%dKB\r\n",
					Cache_Type[GetBitsValue(Value[0],0,4)],GetBitsValue(Value[0],5,7),GetBitsValue(Value[1],22,31),
					((GetBitsValue(Value[1],22,31)+1)*(GetBitsValue(Value[1],12,21)+1)*(GetBitsValue(Value[1],0,11)+1)*(Value[2]+1))>>10);
				OutputStr.Append(OrgStr);
				GetCPUID2(4,2,Value);
				OrgStr.Format("Cache Type:%s,Cache Level:%d,Ways of associativity:%d,Cache Size:%dKB\r\n",
					Cache_Type[GetBitsValue(Value[0],0,4)],GetBitsValue(Value[0],5,7),GetBitsValue(Value[1],22,31),
					((GetBitsValue(Value[1],22,31)+1)*(GetBitsValue(Value[1],12,21)+1)*(GetBitsValue(Value[1],0,11)+1)*(Value[2]+1))>>10);
				OutputStr.Append(OrgStr);				
				OutputStr.Append("\r\n");
				break;
			case 5:
				break;
			case 6:
				for(j=0;j<=6;j++)
				{
					if(j==3)
					{
						continue;
					}
					if(TEST_BIT(Value[0],j))
					{
						OrgStr.Format("%s\r\n",Power_Management[j]);
						OutputStr.Append(OrgStr);
					}
				}
				OutputStr.Append("\r\n");
				break;
			case 0x0B:
				break;
			default:
				break;
		}
	}

	//m_Output.SetWindowText(OutputStr);

	OutputStr.Append("\r\n");
	MaxOperand = 0x80000000;
	for(i=0x80000000;i<=MaxOperand;i++)
	{
		memset(Value,0,sizeof(Value));
		GetCPUID(i,Value);
		OrgStr.Format("EAX Operand 0x%X,0x%08X-0x%08X-0x%08X-0x%08X\r\n",i,Value[0],Value[1],Value[2],Value[3]);
		OutputStr.Append(OrgStr);
		switch(i)
		{
			case 0x80000000:
				MaxOperand = Value[0];
				break;
			case 0x80000002:
			case 0x80000003:
			case 0x80000004:
				OrgStr.Format("%s\r\n",(char*)Value);
				OutputStr.Append(OrgStr);
				if (0x80000004 == i)
				{
					OutputStr.Append("\r\n");
				}
				break;
			default:
				//OrgStr.Format("0x%08X-0x%08X-0x%08X-0x%08X\r\n",Value[0],Value[1],Value[2],Value[3]);
				//OutputStr.Append(OrgStr);
				//OutputStr.Append("\r\n");
				break;
		}
	}

	return OutputStr;
}