<?xml version="1.0" encoding="utf-8" ?><rss version="2.0"><channel><title><![CDATA[smlin04m的博客]]></title><description><![CDATA[]]></description><link>https://blog.youkuaiyun.com/smlin04m</link><language>zh-cn</language><generator>https://blog.youkuaiyun.com/</generator><copyright><![CDATA[Copyright &copy; smlin04m]]></copyright><item><title><![CDATA[【STM32】资料]]></title><link>https://blog.youkuaiyun.com/smlin04m/article/details/123036661</link><guid>https://blog.youkuaiyun.com/smlin04m/article/details/123036661</guid><author>smlin04m</author><pubDate>Sun, 20 Feb 2022 22:11:25 +0800</pubDate><description><![CDATA[MDK5 Software Packs (keil.com)
]]></description><category></category></item><item><title><![CDATA[初学ISE 半加器仿真 VHDL]]></title><link>https://blog.youkuaiyun.com/smlin04m/article/details/102296429</link><guid>https://blog.youkuaiyun.com/smlin04m/article/details/102296429</guid><author>smlin04m</author><pubDate>Mon, 07 Oct 2019 11:54:14 +0800</pubDate><description><![CDATA[选了FPGA的课记录一下怎么搭建工程免得忘了

1、先创建工程





然后记得选ISim 要不然等会仿真的时候会让你使用modelsim的仿真器



完成创建 Finish

2、添加模块



选择new source



然后 VHDL Module



接着输入下面的信息

3、编写VHDL代码



输入以下代码


library IEEE;
use IEEE.STD_LOGI...]]></description><category></category></item><item><title><![CDATA[Verilog HDL 遇到的问题和修改方法]]></title><link>https://blog.youkuaiyun.com/smlin04m/article/details/85051158</link><guid>https://blog.youkuaiyun.com/smlin04m/article/details/85051158</guid><author>smlin04m</author><pubDate>Mon, 17 Dec 2018 16:19:21 +0800</pubDate><description><![CDATA[ 

1.Illegal output port connection for 'Q' (4th connection) to reg type.

我一开始编译的时候是没有问题的但是到了仿真testbanch 的时候就出现了

上一级module Q是这样定义的output reg Q 

然后我这一级调用的时候是reg[2:0] counter

dff_sr U1(.Q(counter[0]...]]></description><category></category></item><item><title><![CDATA[学习ROS（一）：建工作空间]]></title><link>https://blog.youkuaiyun.com/smlin04m/article/details/84920554</link><guid>https://blog.youkuaiyun.com/smlin04m/article/details/84920554</guid><author>smlin04m</author><pubDate>Sun, 09 Dec 2018 15:03:30 +0800</pubDate><description><![CDATA[安装完ROS 后

新建一个目录

mkdir -p catkin_ws/src

建好以后，进入工作空间

cd catkin_ws/

然后编译工作空间     刷新工作环境（记得每次写完代码都要刷新和编译工作环境）

catkin_make

source ~/catkin_ws/devel/setup.bash

但是这样的话编译的东西只在这终端里   如果想打开终端的时候自动添加可以加这...]]></description><category></category></item></channel></rss>