STM32F407ZGT6引脚定义

已于 2025-06-07 12:13:24 修改
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文章标签： stm32 嵌入式硬件 单片机
于 2025-06-07 12:12:10 首次发布
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本文链接：https://blog.youkuaiyun.com/sakitea/article/details/148493574

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<!DOCTYPE html>
<html lang="zh-CN">
<head>
    <meta charset="UTF-8">
    <meta name="viewport" content="width=device-width, initial-scale=1.0">
    <title>STM32F407ZGT6 引脚功能表</title>
    <style>
        body {
            font-family: Arial, sans-serif;
            margin: 20px;
        }
        h1 {
            color: #0066cc;
            text-align: center;
        }
        table {
            width: 100%;
            border-collapse: collapse;
            margin-top: 20px;
        }
        th, td {
            border: 1px solid #ddd;
            padding: 8px;
            text-align: left;
        }
        th {
            background-color: #f2f2f2;
            position: sticky;
            top: 0;
        }
        tr:nth-child(even) {
            background-color: #f9f9f9;
        }
        tr:hover {
            background-color: #f1f1f1;
        }
        .power {
            background-color: #ffdddd;
        }
        .debug {
            background-color: #ddffdd;
        }
        .boot {
            background-color: #ddddff;
        }
        .filter-controls {
            margin-bottom: 15px;
            padding: 10px;
            background-color: #f5f5f5;
            border-radius: 5px;
        }
        .search-box {
            padding: 8px;
            width: 300px;
            margin-right: 10px;
        }
    </style>
</head>
<body>
    <h1>STM32F407ZGT6 引脚功能表</h1>
    
    <div class="filter-controls">
        <input type="text" id="searchInput" class="search-box" placeholder="搜索引脚、功能..." onkeyup="filterTable()">
        <button onclick="resetFilters()">重置筛选</button>
    </div>
    
    <table id="pinTable">
        <thead>
            <tr>
                <th>引脚</th>
                <th>引脚名称</th>
                <th>主功能</th>
                <th>默认复用功能</th>
            </tr>
        </thead>
        <tbody>
            <tr>
                <td>1</td>
                <td>PE2</td>
                <td>PE2</td>
                <td>TRACECLK/ FSMC_A23 /ETH_MII_TXD3 /EVENTOUT</td>
            </tr>
            <tr>
                <td>2</td>
                <td>PE3</td>
                <td>PE3</td>
                <td>TRACED0/FSMC_A19 /EVENTOUT</td>
            </tr>
            <tr>
                <td>3</td>
                <td>PE4</td>
                <td>PE4</td>
                <td>TRACED1/FSMC_A20 /DCMI_D4/ EVENTOUT</td>
            </tr>
            <tr>
                <td>4</td>
                <td>PE5</td>
                <td>PE5</td>
                <td>TRACED2 / FSMC_A21 /TIM9_CH1 / DCMI_D6 /EVENTOUT</td>
            </tr>
            <tr>
                <td>5</td>
                <td>PE6</td>
                <td>PE6</td>
                <td>TRACED3 / FSMC_A22 /TIM9_CH2 / DCMI_D7 /EVENTOUT</td>
            </tr>
            <tr class="power">
                <td>6</td>
                <td>VBAT</td>
                <td>VBAT</td>
                <td>RTC供电引脚</td>
            </tr>
            <tr>
                <td>7</td>
                <td>PC13</td>
                <td>PC13</td>
                <td>RTC_OUT,RTC_TAMP1,RTC_TS</td>
            </tr>
            <tr>
                <td>8</td>
                <td>PC14</td>
                <td>PC14</td>
                <td>OSC32_IN(PC14)</td>
            </tr>
            <tr>
                <td>9</td>
                <td>PC15</td>
                <td>PC15</td>
                <td>OSC32_OUT(PC15)</td>
            </tr>
            <tr>
                <td>10</td>
                <td>PF0</td>
                <td>PF0</td>
                <td>FSMC_A0 / I2C2_SDA /EVENTOUT</td>
            </tr>
            <tr>
                <td>11</td>
                <td>PF1</td>
                <td>PF1</td>
                <td>FSMC_A1 / I2C2_SCL /EVENTOUT</td>
            </tr>
            <tr>
                <td>12</td>
                <td>PF2</td>
                <td>PF2</td>
                <td>FSMC_A2 / I2C2_SMBA /EVENTOUT</td>
            </tr>
            <tr>
                <td>13</td>
                <td>PF3</td>
                <td>PF3</td>
                <td>PF3/FSMC_A3/EVENTOUT/ADC3_IN9</td>
            </tr>
            <tr>
                <td>14</td>
                <td>PF4</td>
                <td>PF4</td>
                <td>PF4/FSMC_A4/EVENTOUT/ADC3_IN14</td>
            </tr>
            <tr>
                <td>15</td>
                <td>PF5</td>
                <td>PF5</td>
                <td>PF5/FSMC_A5/EVENTOUT/ADC3_IN15</td>
            </tr>
            <tr class="power">
                <td>16</td>
                <td>VSS</td>
                <td>VSS</td>
                <td></td>
            </tr>
            <tr class="power">
                <td>17</td>
                <td>VDD</td>
                <td>VDD</td>
                <td></td>
            </tr>
            <tr>
                <td>18</td>
                <td>PF6</td>
                <td>PF6</td>
                <td>TIM10_CH1 /FSMC_NIORD/EVENTOUT/ADC3_IN4</td>
            </tr>
            <tr>
                <td>19</td>
                <td>PF7</td>
                <td>PF7</td>
                <td>PF7/TIM11_CH1/FSMC_NREG/EVENTOUT/ADC3_IN5</td>
            </tr>
            <tr>
                <td>20</td>
                <td>PF8</td>
                <td>PF8</td>
                <td>PF8/TIM13_CH1 /FSMC_NIOWR/EVENTOUT/ADC3_IN6</td>
            </tr>
            <tr>
                <td>21</td>
                <td>PF9</td>
                <td>PF9</td>
                <td>PF9/TIM14_CH1 / FSMC_CD/EVENTOUT/ADC3_IN7</td>
            </tr>
            <tr>
                <td>22</td>
                <td>PF10</td>
                <td>PF10</td>
                <td>PF10/FSMC_INTR/ EVENTOUT /ADC3_IN8</td>
            </tr>
            <tr>
                <td>23</td>
                <td>PH0</td>
                <td>PH0</td>
                <td>OSC_IN(PH0)</td>
            </tr>
            <tr>
                <td>24</td>
                <td>PH1</td>
                <td>PH1</td>
                <td>OSC_OUT(PH1)</td>
            </tr>
            <tr class="debug">
                <td>25</td>
                <td>NRST</td>
                <td>复位</td>
                <td></td>
            </tr>
            <tr>
                <td>26</td>
                <td>PC0</td>
                <td>PC0</td>
                <td>OTG_HS_ULPI_STP/EVENTOUT /ADC123_IN10</td>
            </tr>
            <tr>
                <td>27</td>
                <td>PC1</td>
                <td>PC1</td>
                <td>PC1 / ETH_MDC/ EVENTOUT /ADC123_IN11</td>
            </tr>
            <tr>
                <td>28</td>
                <td>PC2</td>
                <td>PC2</td>
                <td>PC2 /SPI2_MISO /OTG_HS_ULPI_DIR /ETH_MII_TXD2/I2S2ext_SD/ EVENTOUT/ADC123_IN12</td>
            </tr>
            <tr>
                <td>29</td>
                <td>PC3</td>
                <td>PC3</td>
                <td>PC3 /SPI2_MOSI / I2S2_SD /OTG_HS_ULPI_NXT /ETH_MII_TX_CLK/EVENTOUT/ADC123_IN13</td>
            </tr>
            <tr class="power">
                <td>30</td>
                <td>VDD</td>
                <td>VDD</td>
                <td></td>
            </tr>
            <tr class="power">
                <td>31</td>
                <td>VSSA</td>
                <td>VSSA</td>
                <td></td>
            </tr>
            <tr class="power">
                <td>32</td>
                <td>VREF+</td>
                <td>VREF+</td>
                <td></td>
            </tr>
            <tr class="power">
                <td>33</td>
                <td>VDDA</td>
                <td>VDDA</td>
                <td></td>
            </tr>
            <tr>
                <td>34</td>
                <td>PA0</td>
                <td>WKUP(PA0)</td>
                <td>USART2_CTS/UART4_TX/ETH_MII_CRS /TIM2_CH1_ETR/TIM5_CH1 / TIM8_ETR/EVENTOUT/ADC123_IN0/WKUP(4)</td>
            </tr>
            <tr>
                <td>35</td>
                <td>PA1</td>
                <td>PA1</td>
                <td>USART2_RTS /UART4_RX/ETH_RMII_REF_CLK /ETH_MII_RX_CLK /TIM5_CH2 / TIM2_CH2/EVENTOUT/ADC123_IN1</td>
            </tr>
            <tr>
                <td>36</td>
                <td>PA2</td>
                <td>PA2</td>
                <td>USART2_TX/TIM5_CH3 /TIM9_CH1 / TIM2_CH3 /ETH_MDIO/ EVENTOUT/ADC123_IN2</td>
            </tr>
            <tr>
                <td>37</td>
                <td>PA3</td>
                <td>PA3</td>
                <td>USART2_RX/TIM5_CH4 /TIM9_CH2 / TIM2_CH4 /OTG_HS_ULPI_D0 /ETH_MII_COL/EVENTOUT/ADC123_IN3</td>
            </tr>
            <tr class="power">
                <td>38</td>
                <td>VSS</td>
                <td>VSS</td>
                <td></td>
            </tr>
            <tr class="power">
                <td>39</td>
                <td>VDD</td>
                <td>VDD</td>
                <td></td>
            </tr>
            <tr>
                <td>40</td>
                <td>PA4</td>
                <td>PA4</td>
                <td>SPI1_NSS / SPI3_NSS /USART2_CK /DCMI_HSYNC /OTG_HS_SOF/ I2S3_WS/EVENTOUT/ADC12_IN4/DAC_OUT1</td>
            </tr>
            <tr>
                <td>41</td>
                <td>PA5</td>
                <td>PA5</td>
                <td>PA5/SPI1_SCK/OTG_HS_ULPI_CK /TIM2_CH1_ETR/TIM8_CH1N/ EVENTOUT/ADC12_IN5/DAC_OUT2</td>
            </tr>
            <tr>
                <td>42</td>
                <td>PA6</td>
                <td>PA6</td>
                <td>PA6 /SPI1_MISO /TIM8_BKIN/TIM13_CH1 /DCMI_PIXCLK / TIM3_CH1/ TIM1_BKIN/ EVENTOUT/ADC12_IN6</td>
            </tr>
            <tr>
                <td>43</td>
                <td>PA7</td>
                <td>PA7</td>
                <td>PA7/SPI1_MOSI/ TIM8_CH1N /TIM14_CH1/TIM3_CH2/ETH_MII_RX_DV /TIM1_CH1N /ETH_RMII_CRS_DV/EVENTOUT/ADC12_IN7</td>
            </tr>
            <tr>
                <td>44</td>
                <td>PC4</td>
                <td>PC4</td>
                <td>ETH_RMII_RX_D0 /ETH_MII_RX_D0/EVENTOUT/ADC12_IN14</td>
            </tr>
            <tr>
                <td>45</td>
                <td>PC5</td>
                <td>PC5</td>
                <td>PC5 /ETH_RMII_RX_D1 /ETH_MII_RX_D1/EVENTOUT/ADC12_IN15</td>
            </tr>
            <tr>
                <td>46</td>
                <td>PB0</td>
                <td>PB0</td>
                <td>TIM3_CH3 / TIM8_CH2N/OTG_HS_ULPI_D1/ETH_MII_RXD2 /TIM1_CH2N/ EVENTOUT/ADC12_IN8</td>
            </tr>
            <tr>
                <td>47</td>
                <td>PB1</td>
                <td>PB1</td>
                <td>TIM3_CH4 / TIM8_CH3N/OTG_HS_ULPI_D2/ETH_MII_RXD3 /TIM1_CH3N/ EVENTOUT/ADC12_IN9</td>
            </tr>
            <tr class="boot">
                <td>48</td>
                <td>PB2</td>
                <td>BOOT1</td>
                <td></td>
            </tr>
            <tr>
                <td>49</td>
                <td>PF11</td>
                <td>PF11</td>
                <td>DCMI_D12/ EVENTOUT</td>
            </tr>
            <tr>
                <td>50</td>
                <td>PF12</td>
                <td>PF12</td>
                <td>FSMC_A6/ EVENTOUT</td>
            </tr>
            <tr class="power">
                <td>51</td>
                <td>VSS</td>
                <td>VSS</td>
                <td></td>
            </tr>
            <tr class="power">
                <td>52</td>
                <td>VDD</td>
                <td>VDD</td>
                <td></td>
            </tr>
            <tr>
                <td>53</td>
                <td>PF13</td>
                <td>PF13</td>
                <td>FSMC_A7/ EVENTOUT</td>
            </tr>
            <tr>
                <td>54</td>
                <td>PF14</td>
                <td>PF14</td>
                <td>PF14 / FSMC_A8/ EVENTOUT</td>
            </tr>
            <tr>
                <td>55</td>
                <td>PF15</td>
                <td>PF15</td>
                <td>PF15 /FSMC_A9/ EVENTOUT</td>
            </tr>
            <tr>
                <td>56</td>
                <td>PG0</td>
                <td>PG0</td>
                <td>FSMC_A10/ EVENTOUT</td>
            </tr>
            <tr>
                <td>57</td>
                <td>PG1</td>
                <td>PG1</td>
                <td>PG1 / FSMC_A11/ EVENTOUT</td>
            </tr>
            <tr>
                <td>58</td>
                <td>PE7</td>
                <td>PE7</td>
                <td>FSMC_D4/TIM1_ETR/EVENTOUT</td>
            </tr>
            <tr>
                <td>59</td>
                <td>PE8</td>
                <td>PE8</td>
                <td>FSMC_D5/ TIM1_CH1N/EVENTOUT</td>
            </tr>
            <tr>
                <td>60</td>
                <td>PE9</td>
                <td>PE9</td>
                <td>FSMC_D6/TIM1_CH1/EVENTOUT</td>
            </tr>
            <tr class="power">
                <td>61</td>
                <td>VSS</td>
                <td>VSS</td>
                <td></td>
            </tr>
            <tr class="power">
                <td>62</td>
                <td>VDD</td>
                <td>VDD</td>
                <td></td>
            </tr>
            <tr>
                <td>63</td>
                <td>PE10</td>
                <td>PE10</td>
                <td>FSMC_D7/TIM1_CH2N/EVENTOUT</td>
            </tr>
            <tr>
                <td>64</td>
                <td>PE11</td>
                <td>PE11</td>
                <td>FSMC_D8/TIM1_CH2/EVENTOUT</td>
            </tr>
            <tr>
                <td>65</td>
                <td>PE12</td>
                <td>PE12</td>
                <td>FSMC_D9/TIM1_CH3N/EVENTOUT</td>
            </tr>
            <tr>
                <td>66</td>
                <td>PE13</td>
                <td>PE13</td>
                <td>FSMC_D10/TIM1_CH3/EVENTOUT</td>
            </tr>
            <tr>
                <td>67</td>
                <td>PE14</td>
                <td>PE14</td>
                <td>FSMC_D11/TIM1_CH4/EVENTOUT</td>
            </tr>
            <tr>
                <td>68</td>
                <td>PE15</td>
                <td>PE15</td>
                <td>FSMC_D12/TIM1_BKIN/EVENTOUT</td>
            </tr>
            <tr>
                <td>69</td>
                <td>PB10</td>
                <td>PB10</td>
                <td>SPI2_SCK / I2S2_CK /I2C2_SCL/ USART3_TX /OTG_HS_ULPI_D3 /ETH_MII_RX_ER /TIM2_CH3/ EVENTOUT</td>
            </tr>
            <tr>
                <td>70</td>
                <td>PB11</td>
                <td>PB11</td>
                <td>I2C2_SDA/USART3_RX/OTG_HS_ULPI_D4 /ETH_RMII_TX_EN/ETH_MII_TX_EN /TIM2_CH4/ EVENTOUT</td>
            </tr>
            <tr class="power">
                <td>71</td>
                <td>VCAP_1</td>
                <td></td>
                <td>内部LDO电压输出-1.2V</td>
            </tr>
            <tr class="power">
                <td>72</td>
                <td>VDD</td>
                <td>VDD</td>
                <td></td>
            </tr>
            <tr>
                <td>73</td>
                <td>PB12</td>
                <td>PB12</td>
                <td>SPI2_NSS / I2S2_WS /I2C2_SMBA/USART3_CK/ TIM1_BKIN /CAN2_RX /OTG_HS_ULPI_D5/ETH_RMII_TXD0 /ETH_MII_TXD0/OTG_HS_ID/ EVENTOUT</td>
            </tr>
            <tr>
                <td>74</td>
                <td>PB13</td>
                <td>PB13</td>
                <td>SPI2_SCK / I2S2_CK /USART3_CTS/TIM1_CH1N /CAN2_TX /OTG_HS_ULPI_D6 /ETH_RMII_TXD1 /ETH_MII_TXD1/EVENTOUT/OTG_HS_VBUS</td>
            </tr>
            <tr>
                <td>75</td>
                <td>PB14</td>
                <td>PB14</td>
                <td>SPI2_MISO/ TIM1_CH2N /TIM12_CH1 /OTG_HS_DM/USART3_RTS /TIM8_CH2N/I2S2ext_SD/EVENTOUT</td>
            </tr>
            <tr>
                <td>76</td>
                <td>PB15</td>
                <td>PB15</td>
                <td>SPI2_MOSI / I2S2_SD/TIM1_CH3N / TIM8_CH3N/ TIM12_CH2 /OTG_HS_DP/ EVENTOUT/RTC_REFIN</td>
            </tr>
            <tr>
                <td>77</td>
                <td>PD8</td>
                <td>PD8</td>
                <td>FSMC_D13 / USART3_TX/EVENTOUT</td>
            </tr>
            <tr>
                <td>78</td>
                <td>PD9</td>
                <td>PD9</td>
                <td>FSMC_D14 / USART3_RX/EVENTOUT</td>
            </tr>
            <tr>
                <td>79</td>
                <td>PD10</td>
                <td>PD10</td>
                <td>FSMC_D15 / USART3_CK/EVENTOUT</td>
            </tr>
            <tr>
                <td>80</td>
                <td>PD11</td>
                <td>PD11</td>
                <td>FSMC_CLE /FSMC_A16/USART3_CTS/EVENTOUT</td>
            </tr>
            <tr>
                <td>81</td>
                <td>PD12</td>
                <td>PD12</td>
                <td>FSMC_ALE/FSMC_A17/TIM4_CH1 /USART3_RTS/EVENTOUT</td>
            </tr>
            <tr>
                <td>82</td>
                <td>PD13</td>
                <td>PD13</td>
                <td>FSMC_A18/TIM4_CH2/EVENTOUT</td>
            </tr>
            <tr class="power">
                <td>83</td>
                <td>VSS</td>
                <td>VSS</td>
                <td></td>
            </tr>
            <tr class="power">
                <td>84</td>
                <td>VDD</td>
                <td>VDD</td>
                <td></td>
            </tr>
            <tr>
                <td>85</td>
                <td>PD14</td>
                <td>PD14</td>
                <td>FSMC_D0/TIM4_CH3/EVENTOUT/ EVENTOUT</td>
            </tr>
            <tr>
                <td>86</td>
                <td>PD15</td>
                <td>PD15</td>
                <td>FSMC_D1/TIM4_CH4/EVENTOUT</td>
            </tr>
            <tr>
                <td>87</td>
                <td>PG2</td>
                <td>PG2</td>
                <td>FSMC_A12/ EVENTOUT</td>
            </tr>
            <tr>
                <td>88</td>
                <td>PG3</td>
                <td>PG3</td>
                <td>FSMC_A13/ EVENTOUT</td>
            </tr>
            <tr>
                <td>90</td>
                <td>PG5</td>
                <td>PG5</td>
                <td>FSMC_A15/ EVENTOUT</td>
            </tr>
            <tr>
                <td>91</td>
                <td>PG6</td>
                <td>PG6</td>
                <td>FSMC_INT2/ EVENTOUT</td>
            </tr>
            <tr>
                <td>92</td>
                <td>PG7</td>
                <td>PG7</td>
                <td>FSMC_INT3 /USART6_CK/EVENTOUT</td>
            </tr>
            <tr>
                <td>93</td>
                <td>PG8</td>
                <td>PG8</td>
                <td>USART6_RTS /ETH_PPS_OUT/EVENTOUT</td>
            </tr>
            <tr class="power">
                <td>94</td>
                <td>VSS</td>
                <td>VSS</td>
                <td></td>
            </tr>
            <tr class="power">
                <td>95</td>
                <td>VDD</td>
                <td>VDD</td>
                <td></td>
            </tr>
            <tr>
                <td>96</td>
                <td>PC6</td>
                <td>PC6</td>
                <td>I2S2_MCK /TIM8_CH1/SDIO_D6 /USART6_TX /DCMI_D0/TIM3_CH1/EVENTOUT</td>
            </tr>
            <tr>
                <td>97</td>
                <td>PC7</td>
                <td>PC7</td>
                <td>I2S3_MCK /TIM8_CH2/SDIO_D7 /USART6_RX /DCMI_D1/TIM3_CH2/EVENTOUT</td>
            </tr>
            <tr>
                <td>98</td>
                <td>PC8</td>
                <td>PC8</td>
                <td>TIM8_CH3/SDIO_D0/TIM3_CH3/ USART6_CK /DCMI_D2/ EVENTOUT</td>
            </tr>
            <tr>
                <td>99</td>
                <td>PC9</td>
                <td>PC9</td>
                <td>I2S_CKIN/ MCO2 /TIM8_CH4/SDIO_D1 /I2C3_SDA / DCMI_D3 /TIM3_CH4/ EVENTOUT</td>
            </tr>
            <tr>
                <td>100</td>
                <td>PA8</td>
                <td>PA8</td>
                <td>MCO1 / USART1_CK/TIM1_CH1/ I2C3_SCL/OTG_FS_SOF/EVENTOUT</td>
            </tr>
            <tr>
                <td>101</td>
                <td>PA9</td>
                <td>PA9</td>
                <td>USART1_TX/ TIM1_CH2 /I2C3_SMBA / DCMI_D0/EVENTOUT/OTG_FS_VBUS</td>
            </tr>
            <tr>
                <td>102</td>
                <td>PA10</td>
                <td>PA10</td>
                <td>USART1_RX/ TIM1_CH3/OTG_FS_ID/DCMI_D1/EVENTOUT</td>
            </tr>
            <tr>
                <td>103</td>
                <td>PA11</td>
                <td>PA11</td>
                <td>USART1_CTS / CAN1_RX/ TIM1_CH4 /OTG_FS_DM/ EVENTOUT</td>
            </tr>
            <tr>
                <td>104</td>
                <td>PA12</td>
                <td>PA12</td>
                <td>USART1_RTS / CAN1_TX/TIM1_ETR/ OTG_FS_DP/EVENTOUT</td>
            </tr>
            <tr class="debug">
                <td>105</td>
                <td>PA13</td>
                <td>JTMS/SWDIO</td>
                <td></td>
            </tr>
            <tr class="power">
                <td>106</td>
                <td>VCAP_2</td>
                <td></td>
                <td>内部LDO电压-1.2V</td>
            </tr>
            <tr class="power">
                <td>107</td>
                <td>VSS</td>
                <td>VSS</td>
                <td></td>
            </tr>
            <tr class="power">
                <td>108</td>
                <td>VDD</td>
                <td>VDD</td>
                <td></td>
            </tr>
            <tr class="debug">
                <td>109</td>
                <td>PA14</td>
                <td>JTCK/SWCLK</td>
                <td></td>
            </tr>
            <tr class="debug">
                <td>110</td>
                <td>PA15</td>
                <td>JTDI</td>
                <td></td>
            </tr>
            <tr>
                <td>111</td>
                <td>PC10</td>
                <td>PC10</td>
                <td>SPI3_SCK / I2S3_CK/UART4_TX/SDIO_D2 /DCMI_D8 / USART3_TX/EVENTOUT</td>
            </tr>
            <tr>
                <td>112</td>
                <td>PC11</td>
                <td>PC11</td>
                <td>UART4_RX/ SPI3_MISO /SDIO_D3 /DCMI_D4/USART3_RX /I2S3ext_SD/ EVENTOUT</td>
            </tr>
            <tr>
                <td>113</td>
                <td>PC12</td>
                <td>PC12</td>
                <td>UART5_TX/SDIO_CK /DCMI_D9 / SPI3_MOSI/I2S3_SD / USART3_CK/EVENTOUT</td>
            </tr>
            <tr>
                <td>114</td>
                <td>PD0</td>
                <td>PD0</td>
                <td>FSMC_D2/CAN1_RX/EVENTOUT</td>
            </tr>
            <tr>
                <td>115</td>
                <td>PD1</td>
                <td>PD1</td>
                <td>FSMC_D3 / CAN1_TX/EVENTOUT</td>
            </tr>
            <tr>
                <td>116</td>
                <td>PD2</td>
                <td>PD2</td>
                <td>TIM3_ETR/UART5_RX/SDIO_CMD / DCMI_D11/EVENTOUT</td>
            </tr>
            <tr>
                <td>117</td>
                <td>PD3</td>
                <td>PD3</td>
                <td>FSMC_CLK/USART2_CTS/EVENTOUT</td>
            </tr>
            <tr>
                <td>118</td>
                <td>PD4</td>
                <td>PD4</td>
                <td>FSMC_NOE/USART2_RTS/EVENTOUT</td>
            </tr>
            <tr>
                <td>119</td>
                <td>PD5</td>
                <td>PD5</td>
                <td>FSMC_NWE/USART2_TX/EVENTOUT</td>
            </tr>
            <tr class="power">
                <td>120</td>
                <td>VSS</td>
                <td>VSS</td>
                <td></td>
            </tr>
            <tr class="power">
                <td>121</td>
                <td>VDD</td>
                <td>VDD</td>
                <td></td>
            </tr>
            <tr>
                <td>122</td>
                <td>PD6</td>
                <td>PD6</td>
                <td>FSMC_NWAIT/USART2_RX/ EVENTOUT</td>
            </tr>
            <tr>
                <td>123</td>
                <td>PD7</td>
                <td>PD7</td>
                <td>USART2_CK/FSMC_NE1/FSMC_NCE2/ EVENTOUT</td>
            </tr>
            <tr>
                <td>124</td>
                <td>PG9</td>
                <td>PG9</td>
                <td>USART6_RX /FSMC_NE2/FSMC_NCE3/EVENTOUT</td>
            </tr>
            <tr>
                <td>125</td>
                <td>PG10</td>
                <td>PG10</td>
                <td>FSMC_NCE4_1/FSMC_NE3/ EVENTOUT</td>
            </tr>
            <tr>
                <td>126</td>
                <td>PG11</td>
                <td>PG11</td>
                <td>FSMC_NCE4_2 /ETH_MII_TX_EN/ETH _RMII_TX_EN/EVENTOUT</td>
            </tr>
            <tr>
                <td>127</td>
                <td>PG12</td>
                <td>PG12</td>
                <td>FSMC_NE4 /USART6_RTS/EVENTOUT</td>
            </tr>
            <tr>
                <td>128</td>
                <td>PG13</td>
                <td>PG13</td>
                <td>FSMC_A24 /USART6_CTS/ETH_MII_TXD0/ETH_RMII_TXD0/EVENTOUT</td>
            </tr>
            <tr>
                <td>129</td>
                <td>PG14</td>
                <td>PG14</td>
                <td>FSMC_A25 / USART6_TX/ETH_MII_TXD1/ETH_RMII_TXD1/EVENTOUT</td>
            </tr>
            <tr class="power">
                <td>130</td>
                <td>VSS</td>
                <td>VSS</td>
                <td></td>
            </tr>
            <tr class="power">
                <td>131</td>
                <td>VDD</td>
                <td>VDD</td>
                <td></td>
            </tr>
            <tr>
                <td>132</td>
                <td>PG15</td>
                <td>PG15</td>
                <td>USART6_CTS /DCMI_D13/ EVENTOUT</td>
            </tr>
            <tr class="debug">
                <td>133</td>
                <td>PB3</td>
                <td>JTDO</td>
                <td>(JTDO/TRACESWO)/JTDO/ TRACESWO/SPI3_SCK / I2S3_CK /TIM2_CH2 / SPI1_SCK/EVENTOUT</td>
            </tr>
            <tr class="debug">
                <td>134</td>
                <td>PB4</td>
                <td>NJTRST</td>
                <td>SPI3_MISO /TIM3_CH1 / SPI1_MISO /I2S3ext_SD/ EVENTOUT</td>
            </tr>
            <tr>
                <td>135</td>
                <td>PB5</td>
                <td>PB5</td>
                <td>I2C1_SMBA/ CAN2_RX /OTG_HS_ULPI_D7 /ETH_PPS_OUT/TIM3_CH2/ SPI1_MOSI/ SPI3_MOSI /DCMI_D10 / I2S3_SD/EVENTOUT</td>
            </tr>
            <tr>
                <td>136</td>
                <td>PB6</td>
                <td>PB6</td>
                <td>I2C1_SCL/ TIM4_CH1 /CAN2_TX /DCMI_D5/USART1_TX/EVENTOUT</td>
            </tr>
            <tr>
                <td>137</td>
                <td>PB7</td>
                <td>PB7</td>
                <td>I2C1_SDA / FSMC_NL /DCMI_VSYNC /USART1_RX/ TIM4_CH2/EVENTOUT</td>
            </tr>
            <tr class="boot">
                <td>138</td>
                <td>BOOT0</td>
                <td>BOOT0</td>
                <td></td>
            </tr>
            <tr>
                <td>139</td>
                <td>PB8</td>
                <td>PB8</td>
                <td>TIM4_CH3/SDIO_D4/TIM10_CH1 / DCMI_D6 /ETH_MII_TXD3 /I2C1_SCL/ CAN1_RX/EVENTOUT</td>
            </tr>
            <tr>
                <td>140</td>
                <td>PB9</td>
                <td>PB9</td>
                <td>SPI2_NSS/ I2S2_WS /TIM4_CH4/ TIM11_CH1/SDIO_D5 / DCMI_D7 /I2C1_SDA / CAN1_TX/EVENTOUT</td>
            </tr>
            <tr>
                <td>141</td>
                <td>PE0</td>
                <td>PE0</td>
                <td>TIM4_ETR / FSMC_NBL0 /DCMI_D2/ EVENTOUT</td>
            </tr>
            <tr>
                <td>142</td>
                <td>PE1</td>
                <td>PE1</td>
                <td>FSMC_NBL1 / DCMI_D3/EVENTOUT</td>
            </tr>
            <tr class="power">
                <td>143</td>
                <td>PDR_ON</td>
                <td></td>
                <td>Regulator ON/OFF ，必须接VDD</td>
            </tr>
            <tr class="power">
                <td>144</td>
                <td>VDD</td>
                <td>VDD</td>
                <td></td>
            </tr>
        </tbody>
    </table>

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