mt6575 uboot

bootable/bootloader/uboot/arch/arm/cpu/arm_cortexa8/start.S

.globl _start
_start: b reset
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq


_undefined_instruction: .word undefined_instruction
_software_interrupt: .word software_interrupt
_prefetch_abort: .word prefetch_abort
_data_abort: .word data_abort
_not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
_pad: .word 0x12345678 /* now 16*4=64 */
.global _end_vect
_end_vect:


.balignl 16,0xdeadbeef
/*************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * setup Memory and board specific bits prior to relocation.
 * relocate armboot to ram
 * setup stack
 *
 *************************************************************************/


_TEXT_BASE:
.word TEXT_BASE


.globl _armboot_start
_armboot_start:
.word _start


/*
 * These are defined in the board-specific linker script.
 */
.globl _bss_start
_bss_start:
.word __bss_start


.globl _bss_end
_bss_end:
.word _end


#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
.word 0x0badc0de


/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
#endif


/*
 * the actual reset code
 */


reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0, cpsr
bic r0, r0, #0x1f
orr r0, r0, #0xd3
msr cpsr,r0


#if (CONFIG_OMAP34XX)
/* Copy vectors to mask ROM indirect addr */
adr r0, _start @ r0 <- current position of code
add r0, r0, #4 @ skip reset vector
mov r2, #64 @ r2 <- size to copy
add r2, r0, r2 @ r2 <- source end address
mov r1, #SRAM_OFFSET0 @ build vect addr
mov r3, #SRAM_OFFSET1
add r1, r1, r3
mov r3, #SRAM_OFFSET2
add r1, r1, r3
next:
ldmia r0!, {r3 - r10} @ copy from source address [r0]
stmia r1!, {r3 - r10} @ copy to   target address [r1]
cmp r0, r2 @ until source end address [r2]
bne next @ loop until equal */
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
/* No need to copy/exec the clock code - DPLL adjust already done
* in NAND/oneNAND Boot.
*/
bl cpy_clk_code @ put dpll adjust code behind vectors
#endif /* NAND Boot */
#endif
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif


#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: @ relocate U-Boot to RAM
adr r0, _start @ r0 <- current position of code
ldr r1, _TEXT_BASE @ test if we run from flash or RAM
cmp r0, r1 @ don't reloc during debug
beq stack_setup


ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 @ r2 <- size of armboot
add r2, r0, r2 @ r2 <- source end address


copy_loop: @ copy 32 bytes at a time
ldmia r0!, {r3 - r10} @ copy from source address [r0]
stmia r1!, {r3 - r10} @ copy to   target address [r1]
cmp r0, r2 @ until source end addreee [r2]
ble copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */


/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE @ upper 128 KiB: relocated uboot
sub r0, r0, #CONFIG_SYS_MALLOC_LEN @ malloc area
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE @ bdinfo
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 @ leave 3 words for abort-stack
and sp, sp, #~7 @ 8 byte alinged for (ldr/str)d


/* Clear BSS (if any). Is below tx (watch load addr - need space) */
clear_bss:
ldr r0, _bss_start @ find start of bss segment
ldr r1, _bss_end @ stop here
mov r2, #0x00000000 @ clear value
clbss_l:
str r2, [r0] @ clear BSS location
cmp r0, r1 @ are we at the end yet
add r0, r0, #4 @ increment clear index pointer
bne clbss_l @ keep clearing till at end


ldr pc, _start_armboot @ jump to C code


_start_armboot: .word start_armboot

init_fnc_t *init_sequence[] = {
cpu_init, /* basic cpu dependent setup */
dram_init,              /* configure available RAM banks */ /*  change the original init order */
board_init,/* basic board dependent setup */
interrupt_init,/* set up exceptions */
env_init, /* initialize environment */
init_baudrate,/* initialze baudrate settings */
serial_init, /* serial communications setup */
console_init_f,/* stage 1 init of console */
display_banner,/* say that we are here */
display_dram_config,
NULL,
};

void start_armboot (void)

{

for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) 
{
if ((*init_fnc_ptr)() != 0) {
hang ();
}
}

jumptable_init ();

misc_init_r();

mmc_initialize (gd->bd);

mt65xx_bat_init();

mt65xx_disp_power(1);

mt65xx_disp_show_boot_logo();

mt65xx_backlight_on();

mt65xx_sw_env();

for (;;) {
main_loop();
}

}

int board_init (void)
{
  mtk_serial_init();     

  mtk_wdt_init(); // Modify mtk_wdt.h can select dummy function.
  mt6575_pinmux_init();
  gd->bd->bi_arch_number = MACH_TYPE_MT6575; /* board id for linux */
  gd->bd->bi_boot_params = CFG_BOOTARGS_ADDR; /* address of boot parameters */
  
   gd->fb_base = memory_size() - mt65xx_disp_get_vram_size();

    leds_init();
    isink0_init(); //turn on isink0, HW connection must be floating or pull low

    mt65xx_disp_init((void*)gd->fb_base);

    pmic6329_init();

    return 0;
}

int misc_init_r (void)
{
    int ret = 0;

    mt6575_part_init(BLK_NUM(16 * GB));


    boot_mode_select();

   
    mmc_legacy_init(1);
    mt6575_part_dump();


    ret = mboot_common_load_logo((unsigned long)mt65xx_get_logo_db_addr(),CFG_LOGO_NAME);

mt65xx_disp_fill_rect(0, 0, CFG_DISPLAY_WIDTH, CFG_DISPLAY_HEIGHT, 0x0);
mt65xx_disp_power(TRUE);
mt65xx_disp_update(0, 0, CFG_DISPLAY_WIDTH, CFG_DISPLAY_HEIGHT);



}

void boot_mode_select(void)
{

    if (meta_detection())
    {
      return;
    }

    if (factory_detection())
    {
      return;
    }

    if(recovery_detection())
    {
      //**************************************
  //* CHECK IMAGE
  //**************************************
  if(DRV_Reg32(0x40002300)==0xE92D4800)
  {
   printf(" > do recovery_check\n");
  //jump(0x40002300); 
  }
  else
  {
   printf(" > bypass recovery_check\n");
  }
    return;
    }

}