[HDLBits]Exams/2014 q4a

---

module top_module (
    input clk,
    input w, R, E, L,
    output Q
);    wire a,b;
    Mux2_1 inst0 (.w(w),.q(Q),.e(E),.d(a));
    Mux2_1 inst1 (.w(R),.q(a),.e(L),.d(b));
    DFF inst2 (.d(b),.clk(clk),.q(Q),.Q(!Q));
endmodule
module DFF (input d,input clk,output q,output Q);
    always @(posedge clk) begin
        q <= d;
    end
    assign Q =!q;
endmodule

module Mux2_1 (input w,input q,input e,output d);
    always @(*) begin
        if (e) begin
            d = w;
        end
        else begin
            d = q;
        end
    end
endmodule