EE213 Lab3 virtuoso FullAdder&Partial Product Adder design&layout

本文链接：https://blog.youkuaiyun.com/qq_60183616/article/details/145193166

0 前言

1 设计目标

2 FullAdder

3 Partial Product Adder

0 前言

记录一下来到skd上的强度比较大的一门课，数字集成电路2的lab设计还是蛮好的，该帖非详细教程只是单纯的写一些思虑并用作笔记，新手小白欢迎交流，有错勿喷！

1 设计目标

本篇主要设计了一个全加器，并设计了他的最小尺寸版图，也更好的运用了上篇文章中最小版图的画法。之后运用设计好的全加器模块组成一个有符号乘法累加器,如下图所示。

2 FullAdder

2.1 symbol

2.2 schematic

2.3 layout

该处版图部分使用了有源区共用的思想，因此部分的缩小了全加器的面积

2.4 hspice simulation

*full adder
.TEMP 25
.OPTIONS ACCURATE
.OPTIONS POST=2

.GLOBAL vdd!

* YOU SHOULD INCLUDE MODLE FILES
*.INCLUDE *'/NMOS_VTL.inc'
*.INCLUDE *'/PMOS_VTL.inc' 

* YOU SHOULD INCLUDE YOUR NELIST


* YOU SHOULD ADD LOAD CAPACITANCE

* YOU SHOULD GIVE INPUT PATTERNS FOR TEST CASES

* YOU SHOULD GIVE PROPER INPUT PATTERNS FOR MAXIMUM DELAY

.PARAM PERIOD =40NS
.PARAM T0= 0.1NS
.PARAM T1= T0+PERIOD
.PARAM T2= T1+0.1NS
.PARAM STEP= 1PS

VDD   VDD! 0 0.7
VGND  GND! 0 0

.TRAN STEP T2

* YOU SHOULD INCLUDE MODEL FILES

.INCLUDE "/home/centos/PDK/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_ff/NMOS_VTL.inc"
.INCLUDE "/home/centos/PDK/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_ff/PMOS_VTL.inc"


** Library name: myLib
** Cell name: FA01
** View name: schematic
.subckt FA01 a b c cout s
m27 cout net44 vdd! vdd! PMOS_VTL L=50e-9 W=720e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m25 s net55 vdd! vdd! PMOS_VTL L=50e-9 W=720e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m14 net53 a vdd! vdd! PMOS_VTL L=50e-9 W=720e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m13 net53 b vdd! vdd! PMOS_VTL L=50e-9 W=720e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m12 net53 c vdd! vdd! PMOS_VTL L=50e-9 W=720e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m11 vdd! a net83 vdd! PMOS_VTL L=50e-9 W=720e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m10 net83 b net82 vdd! PMOS_VTL L=50e-9 W=720e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m9 net82 c net55 vdd! PMOS_VTL L=50e-9 W=720e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m8 net55 net44 net53 vdd! PMOS_VTL L=50e-9 W=720e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m7 net44 c net034 vdd! PMOS_VTL L=50e-9 W=720e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m5 net85 b vdd! vdd! PMOS_VTL L=50e-9 W=720e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m6 net44 a net85 vdd! PMOS_VTL L=50e-9 W=720e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m4 vdd! b net034 vdd! PMOS_VTL L=50e-9 W=720e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m0 net034 a vdd! vdd! PMOS_VTL L=50e-9 W=720e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m26 cout net44 0 0 NMOS_VTL L=50e-9 W=360e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m24 s net55 0 0 NMOS_VTL L=50e-9 W=360e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m23 0 a net80 0 NMOS_VTL L=50e-9 W=360e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m22 net80 b net81 0 NMOS_VTL L=50e-9 W=360e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m21 net81 c net55 0 NMOS_VTL L=50e-9 W=360e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m20 net54 c 0 0 NMOS_VTL L=50e-9 W=360e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m19 net54 b 0 0 NMOS_VTL L=50e-9 W=360e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m18 net54 a 0 0 NMOS_VTL L=50e-9 W=360e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m17 net55 net44 net54 0 NMOS_VTL L=50e-9 W=360e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m16 net076 b 0 0 NMOS_VTL L=50e-9 W=360e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m15 net44 a net076 0 NMOS_VTL L=50e-9 W=360e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m3 0 b net35 0 NMOS_VTL L=50e-9 W=360e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m2 net35 a 0 0 NMOS_VTL L=50e-9 W=360e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m1 net44 c net35 0 NMOS_VTL L=50e-9 W=360e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
.ends FA01
** End of subcircuit definition.


xi0  a b c cout sum  FA01

Vin1 A gnd PULSE 0v 0.7v 19.9n 0.1n 0.1n 19.9n 40n
Vin2 B gnd PULSE 0v 0.7v 9.9n 0.1n 0.1n 9.9n 20n 
Vin3 C gnd PULSE 0v 0.7v 4.9n 0.1n 0.1n 4.9n 10n
c1 0 cout 10f
c0 sum 0 10f

.MEASURE TRAN DELAY_COUT TRIG V(C) VAL= 0.35  RISE=3 TARG V(COUT) VAL= 0.35 RISE=2

.probe v(a) v(b) v(c)  v(sum) v(cout)

.END